P80C557E4EFB/01,51 NXP Semiconductors, P80C557E4EFB/01,51 Datasheet - Page 70

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P80C557E4EFB/01,51

Manufacturer Part Number
P80C557E4EFB/01,51
Description
IC 80C51 MCU 1024 ROMLESS 80QFP
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet

Specifications of P80C557E4EFB/01,51

Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
40
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P80C557E4EFB/01,51
Manufacturer:
SILICON
Quantity:
459
Part Number:
P80C557E4EFB/01,51
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
1999 Mar 02
Single-chip 8-bit microcontroller
dotted lines
are valid when RD or
WR are active
only active
during a read
from external
data memory
only active
during a write
to external
data memory
external
program
memory
fetch
read or
write of
external data
memory
PORT
OUTPUT
PORT
INPUT
SERIAL
PORT
CLOCK
Purchase of Philips I
to use the components in the I
I
code 9398 393 40011.
WR
XTAL1
ALE
RD
INPUT
PSEN
Port 2
Bus
(Port 0)
Port 2
Bus
(Port 0)
2
C specifications defined by Philips. This specification can be ordered using the
P1 P2
Int.
in
Int.
in
S1
P1 P2
address
A0–A7
address
A0–A7
address A8–A15
S2
One Machine Cycle
Figure 65. Instruction cycle timing
address A8–A15
P1 P2
2
S3
C components conveys a license under the Philips’ I
old data
P1 P2
Int.
in
Int.
in
S4
sampling time of I/O port pins during input (including INT0 and INT1)
P1 P2
address
A0–A7
address
A0–A7
S5
70
2
address A8–A15 or Port2 out
C system provided the system conforms to the
address A8–A15
P83C557E4/P80C557E4/P89C557E4
P1 P2
S6
P1 P2
Int.
in
S1
data output or data input
P1 P2
address
A0–A7
S2
One Machine Cycle
new data
address A8–A15
P1 P2
S3
P1 P2
Int.
in
S4
P1 P2
address
A0–A7
address
A0–A7
address A8–A15
address A8–A15
S5
P1 P2
S6
2
Product specification
C patent

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