W364M72V-100SBM White Electronic Designs, W364M72V-100SBM Datasheet

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W364M72V-100SBM

Manufacturer Part Number
W364M72V-100SBM
Description
Manufacturer
White Electronic Designs
Datasheet

Specifications of W364M72V-100SBM

Lead Free Status / Rohs Status
Supplier Unconfirmed
64Mx72 Synchronous DRAM
FEATURES
Microsemi Corporation reserves the right to change products or specifi cations without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 4
This product is subject to change without notice.
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on positive edge
of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 64M x 72
Weight: W364M72V-XSBX - TBD grams typical
22.3
TSOP
11.9
54
SAVINGS — Area: 66%
Area 9 x 265mm
TSOP
11.9
54
Area = 800mm
TSOP
11.9
54
2
= 2,385mm
DENSITY COMPARISONS
Discrete Approach (mm)
TSOP
11.9
54
W364M72V-XSBX
2
2
W364M72V-XSBX
32
TSOP
1
11.9
54
I/O Count =
BENEFITS
GENERAL DESCRIPTION
The 512MByte (4.5Gb) SDRAM is a high-speed CMOS, dynamic
random-access, memory using 9 chips containing 512M bits.
Each chip is internally confi gured as a quad-bank DRAM with a
synchronous interface. Each of the chip’s 134,217,728-bit banks
is organized as 8,192 rows by 2,048 columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-12 select the row). The address bits registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
I/O Count
66% SPACE SAVINGS
Reduced part count from 9 to 1
Reduced I/O count
• 55% I/O Reduction
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
TSOP
25
11.9
54
9 x 54 pins = 486 pins
219 Balls
I/O Count: 55%
TSOP
11.9
54
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
TSOP
11.9
W364M72V-XSBX
54
TSOP
11.9
54
Continued on page 4
www.microsemi.com

Related parts for W364M72V-100SBM

W364M72V-100SBM Summary of contents

Page 1

... Commercial, Industrial and Military Temperature Ranges   Organized as 64M x 72   Weight: W364M72V-XSBX - TBD grams typical This product is subject to change without notice. SAVINGS — Area: 66% 11.9 11 22.3 TSOP TSOP Area 9 x 265mm Microsemi Corporation reserves the right to change products or specifi ...

Page 2

... DNU DNU DNU CCQ CCQ DQMH0 0 1 CLK NC 0 CKE CCQ CCQ CAS # RAS # CKE NC CLK CAS # WE 3 DQML3 CCQ CCQ 2 W364M72V-XSBX CCQ CCQ DQML1 24 SS RAS # CLK 1 1 DQMH1 1 SS CAS # CKE Vss CCQ CCQ CC NC CKE V RAS # CLK V WE ...

Page 3

... WE# RAS# CAS 0-1 CLK 3 IC3 CKE 3 # CS# 3 DQM WE# RAS# CAS 0-1 CLK 4 IC4 CKE 4 # CS# 4 DQM W364M72V-XSBX WE# RAS# CAS 0-1 CLK CLK 0 IC5 CKE CKE CS# 0 DQMH DQM WE# RAS# CAS 0-1 CLK CLK 1 IC6 CKE CKE CS# ...

Page 4

... M4-M6 specify the FIGURE 3 – MODE REGISTER DEFINITION Reserved Mode *Should program M12, M11, M10 = ensure compatibility with future devices. and Microsemi Corporation • (602) 437-1520 • www.whiteedc.com W364M72V-XSBX Address Bus Mode Register (Mx) CAS Latency BT Burst Length Burst Length ...

Page 5

... Reserved states should not be used as unknown tion or incompatibility with future versions may result. Microsemi Corporation reserves the right to change products or specifi cations without notice. February 2011 © 2011 Microsemi Corporation. All rights reserved. Rev. 4 W364M72V-XSBX TABLE 1 – BURST DEFINITION Order of Accesses Within a Burst Burst Starting Column ...

Page 6

... AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for sub se quent accesses. Input data appearing on 6 W364M72V-XSBX DON'T CARE UNDEFINED T4 OH Microsemi Corporation • (602) 437-1520 • www.whiteedc.com ...

Page 7

... RE FRESH command will meet the refresh re quire ment and ensure that each row is re freshed. Al ter na tive ly, 8,192 AUTO RE FRESH com mands can be is sued in a burst at the minimum cycle rate (t ), once every refresh period ( Microsemi Corporation • (602) 437-1520 • www.whiteedc.com W364M72V-XSBX ADDR I/ Bank/Row ...

Page 8

... Self refresh available in commercial and industrial tem per a tures only. ABSOLUTE MAXIMUM RATINGS - 4.6 -55 to +125 -40 to +85 -55 to +125 CAPACITANCE (NOTE 2) Symbol CI1 CA CI2 CIO BGA THERMAL RESISTANCE Symbol Theta JA Theta JB Theta JC 8 W364M72V-XSBX Unit V V °C °C °C Max Unit Max Unit TBD ...

Page 9

... T CC CCQ Symbol (All other pins not under test = 0V ≤ OUT CCQ ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13 +3.3V ± 0.3V; -55°C ≤ CCQ 9 W364M72V-XSBX ≤+125°C A Min Max 3 3.6 CCQ 0 -0 2.4 – OH – ...

Page 10

... OHN t 50 120,000 RAS RCD t 64 REF t 16 REF t 70 RFC RRD t 0.3 1.2 T (23) 1 CLK + 7ns t WR (24 XSR 10 W364M72V-XSBX -125 -133 Min Max Min Max 6 5 0.8 2 1.5 3 2.5 3 2 0.8 2 1.5 1 0.8 2 1.5 1 0.8 2 1 1.8 1 ...

Page 11

... Auto precharge mode only. The precharge timing budget (t clock delay, after the last WRITE is executed. 24. Precharge mode only. 25. JEDEC and PC100 specify three clocks. 26. Parameter guaranteed by design. 27. Self refresh available in commercial and industrial temperatures only. 11 W364M72V-XSBX Symbol -100 -125 -133 ...

Page 12

... Microsemi Corporation reserves the right to change products or specifi cations without notice. February 2011 © 2011 Microsemi Corporation. All rights reserved. Rev. 4 Bottom View 32.1 (1.264) MAX 219 x Ø 0.762 (0.030) NOM 19.05 (0.750) NOM ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 12 W364M72V-XSBX ...

Page 13

... Microsemi Corporation reserves the right to change products or specifi cations without notice. February 2011 © 2011 Microsemi Corporation. All rights reserved. Rev. 4 ORDERING INFORMATION W 3 64M XXX SB X -55°C to +125°C -40°C to +85°C 0°C to +70°C 13 W364M72V-XSBX Microsemi Corporation • (602) 437-1520 • www.whiteedc.com www.microsemi.com ...

Page 14

... Microsemi Corporation reserves the right to change products or specifi cations without notice. February 2011 © 2011 Microsemi Corporation. All rights reserved. Rev. 4 Release Date May 2004 January 2005 September 2005 January 2008 February 2011 14 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com W364M72V-XSBX Status Advanced Advanced Preliminary Final Final www.microsemi.com ...

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