W364M72V-100SBM White Electronic Designs, W364M72V-100SBM Datasheet - Page 5

• Manufacturer Part Number: W364M72V-100SBM
• Manufacturer: White Electronic Designs

Specifications of W364M72V-100SBM

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CAS latency, M7 and M8 specify the op er at ing mode, M9 spec i fi es
the WRITE burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefi ned but should be driven LOW
during loading of the mode register.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specifi ed time before ini ti at ing the
subsequent operation. Violating either of these requirements will
result in unspecifi ed operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Fig ure 3. The
burst length determines the maximum number of column lo ca tions
that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4 or 8 locations are avail able for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown op er a tion or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of col umns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, mean ing that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected by A1-9, A11 when the burst length is set to two; by A2-9,
A11 when the burst length is set to four; and by A3-9, A11 when
the burst length is set to eight. The remaining (least signifi cant)
address bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the boundary
is reached.BURST TYPE
Accesses within a given burst may be pro grammed to be either
se quen tial or interleaved; this is re ferred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is de ter mined by the burst
length, the burst type and the start ing column address, as shown
in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the avail abil i ty of the fi rst
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle ear li er
(n + m - 1), and provided that the rel e vant access times are met,
the data will be valid by clock edge n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the latency is
pro grammed to two clocks, the I/Os will start driving after T1 and
the data will be valid by T2. Table 2 below indicates the op er at ing
fre quen cies at which each CAS latency setting can be used.
Reserved states should not be used as unknown op er a tion or
incompatibility with future versions may result.
Microsemi Corporation reserves the right to change products or specifi cations without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 4
5
NOTES:
1. For full-page accesses: y = 2,048.
2. For a burst length of two, A1-9, A11 select the block-of-two burst; A0 selects the starting column
3. For a burst length of four, A2-9, A11 select the block-of-four burst; A0-1 select the starting
4. For a burst length of eight, A3-9, A11 select the block-of-eight burst; A0-2 select the starting
5. For a full-page burst, the full row is selected and A0-9, A11 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
7. For a burst length of one, A0-9, A11 select the unique column to be accessed, and Mode
OPERATING MODE
The nor mal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are re served
for future use and/or test modes. The pro grammed burst length
applies to both READ and WRITE bursts.
Test modes and reserved states should not be used be cause
unknown operation or incompatibility with future versions may
result.
Length
Burst
Page
Full
within the block.
column within the block.
column within the block.
access wraps within the block.
Register bit M3 is ignored.
(y)
2
4
8
SPEED
-100
-125
-133
A2
Starting Column
0
0
0
0
1
1
1
1
(location 0-y)
TABLE 1 – BURST DEFINITION
Address
n = A 0-9
A1
A1
TABLE 2 – CAS LATENCY
0
0
1
1
0
0
1
1
0
0
1
1
LATENCY = 2
A0
A0
A0
0
1
0
1
1
0
1
0
1
0
1
0
1
Microsemi Corporation • [phone] • www.whiteedc.com
0
 100
 100
 75
CAS
Type = Sequential
ALLOWABLE OPERATING
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
FREQUENCY (MHz)
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
W364M72V-XSBX
Cn…
0-1
1-0
LATENCY = 3
Type = In ter leaved
 100
 125
 133
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
CAS
www.microsemi.com
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0