W364M72V-100SBM White Electronic Designs, W364M72V-100SBM Datasheet - Page 8

• Manufacturer Part Number: W364M72V-100SBM
• Manufacturer: White Electronic Designs

Specifications of W364M72V-100SBM

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in
the self refresh mode, the SDRAM retains data with out external
clocking. The SELF RE FRESH command is ini ti at ed like an AUTO
REFRESH com mand except CKE is dis abled (LOW). Once the
SELF RE FRESH command is reg is tered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
minimum period equal to tRAS and may remain in self refresh
mode for an indefi nite period beyond that.
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions
greater than those in di cat ed in the operational sections of this specifi cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.
NOTE:
Refer to Application Note “PBGA Thermal Resistance Correlation” at www.whiteedc.com in the application notes section for modeling conditions.
Microsemi Corporation reserves the right to change products or specifi cations without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 4
Parameter
Voltage on V
Voltage on NC or I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
Description
Junction to Ambient (No Airfl ow)
Junction to Ball
Junction to Case (Top)
CC
, V
CCQ
Supply relative to Vss
ABSOLUTE MAXIMUM RATINGS
BGA THERMAL RESISTANCE
CAPACITANCE
(NOTE 2)
8
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defi ned as a
signal cycling within timing con straints spec i fi ed for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands is sued (a minimum of two clocks) for
t
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH com mands
must be issued as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
* Self refresh available in commercial and industrial tem per a tures only.
XSR
, because time is required for the com ple tion of any internal
Theta JB
Theta JC
Theta JA
Symbol
Symbol
CIO
CI1
CI2
CA
-55 to +125
-55 to +125
-40 to +85
-1 to 4.6
-1 to 4.6
Microsemi Corporation • [phone] • www.whiteedc.com
Max
Max
TBD
TBD
TBD
12
50
12
12
W364M72V-XSBX
Unit
°C
°C
°C
V
V
www.microsemi.com
Unit
Unit
C/W
C/W
C/W
pF
pF
pF
pF