W364M72V-100SBM White Electronic Designs, W364M72V-100SBM Datasheet - Page 7

• Manufacturer Part Number: W364M72V-100SBM
• Manufacturer: White Electronic Designs

Specifications of W364M72V-100SBM

• Lead Free Status / Rohs Status: Supplier Unconfirmed

NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 defi ne the op-code written to the Mode Register and A12 should be driven low.
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-9, A11 provide column address; A10 HIGH enables the auto precharge feature
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
the I/Os is written to the memory array subject to the DQM input
logic level ap pear ing co in ci dent with the data. If a given DQM
signal is registered LOW, the cor re spond ing data will be written to
memory; if the DQM signal is registered HIGH, the cor re spond ing
data inputs will be ignored, and a WRITE will not be executed to
that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row access a specifi ed time (tRP)
after the PRECHARGE command is is sued. Input A10 determines
wheth er one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select
the bank. Oth er wise BA0, BA1 are treated as “Don’t Care.” Once
a bank has been precharged, it is in the idle state and must be
activated pri or to any READ or WRITE commands being is sued
to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same in di vid u al-
bank PRECHARGE function de scribed above, with out re quir ing an
explicit command. This is ac com plished by using A10 to enable
AUTO PRECHARGE in conjunction with a spe cifi c READ or WRITE
command. A precharge of the bank/row that is ad dressed with
the READ or WRITE com mand is au to mat i cal ly performed upon
com ple tion of the READ or WRITE burst, except in the full-page
burst mode, where AUTO PRECHARGE does not ap ply. AUTO
Microsemi Corporation reserves the right to change products or specifi cations without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 4
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which
bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
TRUTH TABLE – COMMANDS AND DQM OPERATION
CS#
H
(NOTE 1)
L
L
L
L
L
L
L
L
–
–
7
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock
PRECHARGE is non per sis tent in that it is either enabled or disabled
for each in di vid u al READ or WRITE com mand.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. The user must not is sue another
command to the same bank until the precharge time (t
This is determined as if an explicit PRECHARGE com mand was
issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fi xed-length or full-page bursts. The most recently reg is tered READ
or WRITE command prior to the BURST TER MI NATE command
will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal op er a tion of the SDRAM
and is analagous to CAS#-BEFORE-RAS# (CBR) RE FRESH in
con ven tion al DRAMs. This com mand is nonpersistent, so it must
be issued each time a refresh is required.
The addressing is generated by the internal refresh con trol ler. This
makes the address bits “Don’t Care” during an AUTO RE FRESH
command. Each 512Mb SDRAM requires 8,192 AUTO RE FRESH
cycles every refresh period (t
RE FRESH command will meet the refresh re quire ment and ensure
that each row is re freshed. Al ter na tive ly, 8,192 AUTO RE FRESH
com mands can be is sued in a burst at the minimum cycle rate
(t
RAS#
RC
X
H
H
H
–
–
L
H
L
L
L
CKE.
delay).
), once every refresh period (t
CAS#
X
H
H
H
H
L
L
L
L
–
–
WE#
H
H
H
H
X
–
–
L
L
L
L
Microsemi Corporation • [phone] • www.whiteedc.com
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
REF
8
8
). Pro vid ing a dis trib ut ed AUTO
REF
W364M72V-XSBX
).
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
RP
www.microsemi.com
) is completed.
High-Z
Active
Active
Valid
I/Os
X
X
X
X
X
X
X