PHKD13N03LT,118 NXP Semiconductors, PHKD13N03LT,118 Datasheet - Page 9
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PHKD13N03LT,118
Manufacturer Part Number
PHKD13N03LT,118
Description
MOSFET N-CH TRENCH DL 30V 8SOIC
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet
1.PHKD13N03LT518.pdf
(13 pages)
Specifications of PHKD13N03LT,118
Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
20 mOhm @ 8A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
10.4A
Vgs(th) (max) @ Id
2V @ 250µA
Gate Charge (qg) @ Vgs
10.7nC @ 5V
Input Capacitance (ciss) @ Vds
752pF @ 15V
Power - Max
3.57W
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
7. Package outline
Fig 14. Package outline SOT96-1 (SO8)
PHKD13N03LT
Product data sheet
SO8: plastic small outline package; 8 leads; body width 3.9 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
inches
UNIT
mm
VERSION
OUTLINE
SOT96-1
0.069
max.
1.75
A
0.010
0.004
0.25
0.10
A
1
0.057
0.049
1.45
1.25
A
076E03
2
IEC
1
8
Z
pin 1 index
0.25
0.01
A
y
3
e
0.019
0.014
0.49
0.36
b
p
D
0.0100
0.0075
All information provided in this document is subject to legal disclaimers.
0.25
0.19
MS-012
JEDEC
c
b
REFERENCES
p
0.20
0.19
D
5.0
4.8
5
4
0
(1)
Rev. 03 — 27 April 2010
w
0.16
0.15
E
4.0
3.8
(2)
M
JEITA
scale
1.27
0.05
2.5
c
e
A
0.244
0.228
2
H
6.2
5.8
A
E
1
0.041
1.05
Dual N-channel TrenchMOS logic level FET
5 mm
L
H
0.039
0.016
E
E
1.0
0.4
detail X
L
p
L
0.028
0.024
L
0.7
0.6
Q
p
Q
PROJECTION
PHKD13N03LT
(A )
EUROPEAN
0.25
0.01
3
A
v
θ
0.25
0.01
A
w
X
v
M
0.004
0.1
A
© NXP B.V. 2010. All rights reserved.
y
ISSUE DATE
99-12-27
03-02-18
0.028
0.012
Z
0.7
0.3
(1)
SOT96-1
8
0
θ
o
o
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