KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 128

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Design Information
20.3
Every system application has different conditions that the thermal management solution must solve. As
such, providing a recommended heat sink has not been found to be very useful. When a heat sink is chosen,
give special consideration to the mounting technique. Mounting the heat sink to the printed-circuit board
is the recommended procedure using a maximum of 10 lbs force (45 Newtons) perpendicular to the
package and board. Clipping the heat sink to the package is not recommended.
21 System Design Information
This section provides electrical design recommendations for successful application of the MPC8548E.
21.1
This device includes five PLLs, as follows:
21.2
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
level should always be equivalent to V
through a low frequency filter scheme such as the following.
128
Die junction-to-case
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
the top surface of the board near the package.
1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the
interface layer.
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
2. The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
3. The PCI PLL generates the clocking for the PCI bus.
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes block.
DD
_PLAT, AV
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in
Heat Sink Solution
System Clocking
PLL Power Supply Filtering
Characteristic
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
DD
Table 81. Package Thermal Characteristics for FC-PBGA (continued)
_CORE, AV
DD
_PCI, AV
DD
Section 19.2, “CCB/SYSCLK PLL Ratio.”
Section 19.3, “e500 Core PLL Ratio.”
, and preferably these voltages are derived directly from V
JEDEC Board
DD
_LBIU, and AV
N/A
DD
Symbol
_SRDS, respectively). The AV
R
θ
JC
Value
0.8
Freescale Semiconductor
°C/W
Unit
Notes
DD
4
DD