KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 59

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 50
frequency in synchronous mode is 110 MHz.
Freescale Semiconductor
HRESET to PCI-X initialization pattern hold time
Notes:
1. See the timing measurement conditions in the PCI-X 1.0a Specification.
2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and
3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t
7. A PCI-X device is permitted to have the minimum values shown for t
8. Device must meet this specification independent of how many outputs switch simultaneously.
9. The timing parameter t
10.Guaranteed by characterization.
11.Guaranteed by design.
SYSCLK to signal valid delay
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup time to SYSCLK
Input hold time from SYSCLK
REQ64 to HRESET setup time
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
PCI-X initialization pattern to HRESET setup time
load circuit.
through the component pin is less than or equal to the leakage current specification.
The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks
before the first FRAME and must be floated no later than one clock before FRAME is asserted.
mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.
provides the PCI-X AC timing specifications at 133 MHz. Note that the maximum PCI-X
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Table 49. PCI-X AC Timing Specifications at 66 MHz (continued)
Parameter
PCRHFV
Parameter
Table 50. PCI-X AC Timing Specifications at 133 MHz
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification.
t
Symbol
t
t
t
Symbol
t
t
t
t
PCKHOV
t
t
PCRHRX
PCKHOX
PCKHOZ
PCRVRH
PCRHFV
PCIVRH
PCRHIX
PCIVKH
PCIXKH
PCKHOV
and t
Min
Min
0.7
1.2
0.5
10
10
10
—
—
0
0
CYC
only in PCI-X mode. In conventional
Max
Max
3.8
50
50
—
—
—
—
—
—
7
clocks
clocks
clocks
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
1, 2, 3, 7, 8
1, 4, 8, 12
3, 5, 9, 11
Notes
10, 12
Notes
1, 11
6, 11
PCRHFV
11
12
12
12
PCI/PCI-X
).
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