M25P20-VMN3TPB Micron Technology Inc, M25P20-VMN3TPB Datasheet - Page 12

• Manufacturer Part Number: M25P20-VMN3TPB
• Manufacturer: Micron Technology Inc

Specifications of M25P20-VMN3TPB

• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 125C
• Package Type: SO N
• Program/erase Volt (typ): 2.3 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

4.5
4.6
12/55
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits, as shown in
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see
Protection Modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P20 features the following data protection mechanisms:
Power On Reset and an internal timer (t
inadvertant changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertant Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Section 6.4: Read Status Register
PUW
) can provide protection against
(RDSR).
Table
6, that