DS21554LB+ Maxim Integrated Products, DS21554LB+ Datasheet - Page 39

• Manufacturer Part Number: DS21554LB+
• Description: IC TXRX E1 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554LB+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 1.544 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
SYMBOL
(MSB)
TESE
TCBFS
TIRFS
RCLA
RSRE
THSE
TBCS
TESE
-
TCBFS
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TIRFS
Transmit-Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select. See Section
details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e., Per-
Cannel Loopback function)
Not Assigned. Should be set to zero when written to.
Receive-Side Signaling Reinsertion Enable. See Section
0 = do not reinsert signaling bits into the data stream presented at the
RSER pin
1 = reinsert the signaling bits into data stream presented at the RSER pin
Transmit-Side Hardware Signaling Insertion Enable. See Section
for details.
0 = do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin
1 = insert signaling from the TSIG pin into the data stream presented at
the TSER pin
Transmit-Side Backplane Clock Select.
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz/4.096MHz/8.192MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0 = RCL declared upon 255 consecutive zeros (125ms)
1 = RCL declared upon 2048 consecutive zeros (1ms)
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NAME AND DESCRIPTION
RSRE
THSE
TBCS
10.2
10.1
for details.
RCLA
(LSB)
for
10.1