DS21554LB+ Maxim Integrated Products, DS21554LB+ Datasheet - Page 76

• Manufacturer Part Number: DS21554LB+
• Description: IC TXRX E1 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554LB+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 1.544 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex)
Note: The RABT, RCRCE, ROVR, and RVM bits are latched and are cleared when read.
RHFR: RECEIVE HDLC FIFO REGISTER (Address = B4 Hex)
SYMBOL
SYMBOL
(MSB)
RABT
REMPTY
HDLC7
(MSB)
RCRCE
OBYTE
CBYTE
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
ROVR
RABT
RVM
POK
RCRCE
HDLC6
POSITION
POSITION
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
RHIR.7
RHIR.6
RHIR.5
RHIR.4
RHIR.3
RHIR.2
RHIR.1
RHIR.0
ROVR
HDLC5
Abort Sequence Detected. Set whenever the HDLC controller sees 7 or
more ones in a row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write a byte
into an already full receive FIFO.
Valid Message. Set when the HDLC controller has detected and checked
a complete HDLC packet.
Empty. A real-time bit that is set high when the receive FIFO is empty.
Packet OK. Set when the byte available for reading in the receive FIFO at
RHFR is the last byte of a valid message (and hence no abort was seen, no
overrun occurred, and the CRC was correct).
Closing Byte. Set when the byte available for reading in the receive FIFO
at RHFR is the last byte of a message (whether the message was valid or
not).
Opening Byte. Set when the byte available for reading in the receive
FIFO at RHFR is the first byte of a message.
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
RVM
HDLC4
REMPTY
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NAME AND DESCRIPTION
NAME AND DESCRIPTION
HDLC3
POK
HDLC2
CBYTE
HDLC1
OBYTE
(LSB)
HDLC0
(LSB)