DS21554LB+ Maxim Integrated Products, DS21554LB+ Datasheet - Page 77
![IC TXRX E1 5V 100-LQFP](/photos/6/82/68291/406-100-lqfp_sml.jpg)
DS21554LB+
Manufacturer Part Number
DS21554LB+
Description
IC TXRX E1 5V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2154LNA2.pdf
(124 pages)
Specifications of DS21554LB+
Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
Remote and AIS Alarm Detector / Generator
Product
Framer
Number Of Transceivers
1
Data Rate
1.544 Mbps
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Supply Current (max)
75 mA (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Ic Interface Type
Parallel, Serial
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LQFP
No. Of Pins
100
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 77 of 124
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THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex)
Note: The TUDR bit is latched and is cleared when read.
THFR: TRANSMIT HDLC FIFO REGISTER (Address = B7 Hex)
SYMBOL
SYMBOL
TEMPTY
HDLC7
(MSB)
(MSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
TFULL
TUDR
—
—
—
—
—
—
HDLC6
POSITION
POSITION
THFR.7
THFR.6
THFR.5
THFR.4
THFR.3
THFR.2
THFR.1
THFR.0
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
THIR.1
THIR.0
—
HDLC5
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Transmit FIFO Empty. A real-time bit that is set high when the FIFO is
empty.
Transmit FIFO Full. A real-time bit that is set high when the FIFO is
full.
Transmit FIFO Underrun. Set when the transmit FIFO empties out
without the TEOM control bit being set. An abort is automatically sent.
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
—
HDLC4
—
77 of 124
NAME AND DESCRIPTION
NAME AND DESCRIPTION
HDLC3
—
TEMPTY
HDLC2
HDLC1
TFULL
HDLC0
TUDR
(LSB)
(LSB)
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