DS26504L+ Maxim Integrated Products, DS26504L+ Datasheet - Page 14

• Manufacturer Part Number: DS26504L+
• Description: IC T1/E1/J1 64KCC ELEMENT 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS26504L+

• Function: BITS Element
• Interface: 64KCC, E1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Includes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

4. PIN FUNCTION DESCRIPTION
4.1 Transmit PLL
4.2 Transmit Side
PLL_OUT
TS_8K_4
TNEGO
TCLKO
TPOSO
NAME
NAME
TCLK
TSER
TYPE
TYPE
I/O
O
O
O
O
I
I
Transmit PLL Output. This pin can be selected to output the 1544kHz,
2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal
signal, TX CLOCK. See
Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary
clock. May be selected by the TX PLL mux to either directly drive the transmit
section or be converted to one of the other rates prior to driving the transmit
section. See
Transmit Serial Data. Source of transmit data sampled on the falling edge of
TX CLOCK (an internal signal). See
timing diagram
TSYNC, 8kHz Sync, 400Hz Sync. See
diagram
T1/E1 Mode: In input mode, this pin is sampled on the falling edge of TX
CLOCK (an internal signal) and a pulse at this pin will establish either frame or
multiframe boundaries for the transmit side.
In output mode, this pin is updated on the rising edge of TX CLOCK (an internal
signal) and can be programmed to output a frame or multiframe sync pulse
useful for aligning data.
64KCC Mode: In input mode, this pin is sampled on the falling edge of TX
CLOCK (an internal signal) and will establish the boundary for the 8kHz portion
of the Composite Clock or the 400Hz boundary based on the setting of IOCR1.3.
In output mode, this pin is updated on the rising edge of TX CLOCK (an internal
signal) and will indicate the 8kHz or 400Hz composite clock alignment.
Transmit Clock Output. Buffered clock that is used to clock data through the
transmit-side formatter (i.e., either TCLK or RCLK).
Payload Mode: When payload mode is enabled, this pin outputs a gapped clock
based on the signal selected for transmit clock. In T1 operation, the clock is
gapped during the F-bit position. In E1 mode, the clock is gapped during time
slots 0 and 16.
Transmit Positive-Data Output. In T1 or E1 mode, updated on the rising edge
of TCLKO with the bipolar data out of the transmit-side formatter. Can be
programmed to source NRZ data via the output-data format (IOCR1.0) control
bit. In 64KCC or 6312kHz mode this pin will be low.
Transmit Negative-Data Output. In T1 or E1 mode, updated on the rising edge
of TCLKO with the bipolar data out of the transmit-side formatter. In 64KCC or
6312kHz mode this pin is low.
(Figure
Figure 3-3
(Figure
20-11).
14 of 129
and
20-11).
Figure 3-3
Figure
FUNCTION
FUNCTION
3-4.
and
Figure
Figure
Figure 3-1
3-1,
3-4.
Figure
and the transmit timing
3-3, and the transmit