SI3201-KS Silicon Laboratories Inc, SI3201-KS Datasheet - Page 55

• Manufacturer Part Number: SI3201-KS
• Description: IC LINEFEED INTRFC SI321X 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3201-KS

• Package / Case: 16-SOIC (3.9mm Width) Exposed Pad, 16-eSOIC, 16-HSOIC
• Function: CODEC
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 5.25 V
• Current - Supply: 88mA
• Power (watts): 800mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: BORSCHT Functions, Ring Trip Detection
• Product: SLIC
• Supply Voltage (min): 3.13 V
• Supply Current: 88 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.12. PCM Interface
The ProSLIC contains a flexible programmable interface
for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK
and FSYNC inputs as well as PCM Mode Select (direct
Register 1),
registers 2 and 3), and PCM Receive Start Count (direct
registers 4 and 5). The interface can be configured to
support from 4 to 128 8-bit timeslots in each frame. This
corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power of 2 increments. (768 kHz and
1.536 MHz are also available, but these frequencies are
not valid for GCI mode.) Timeslots for data transmission
and reception are independently configured using the
TXS and RXS registers. By setting the correct starting
point of the data, the ProSLIC can be configured to
support long FSYNC and short FSYNC variants as well
as IDL2 8-bit, 10-bit, B1 and B2 channel time slots. DTX
data is high-impedance except for the duration of the 8-
bit PCM transmit.
PCM
PCLK_CNT
PCLK_CNT
FSYNC
FSYNC
PCLK
DRX
DTX
PCLK
DRX
DTX
Figure 29. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Transmit
HI-Z
HI-Z
0
0
MSB
MSB
Start
1
1
MSB
MSB
2
2
Count
3
3
4
4
5
5
(direct
Rev. 1.45
6
6
7
7
DTX will return to high impedance either on the negative
edge of PCLK during the LSB or on the positive edge of
PCLK following the LSB. This is based on the setting of
the TRI bit of the PCM Mode Select register. Tristating
on the negative edge allows the transmission of data by
multiple sources in adjacent timeslots without the risk of
driver contention. In addition to 8-bit data modes, there
is a 16-bit mode provided. This mode can be activated
via the PCMT bit of the PCM Mode Select register. GCI
timing is also supported in which the duration of a data
bit is two PCLK cycles. This mode is also activated via
the PCM Mode Select register. Setting the TXS or RXS
register greater than the number of PCLK cycles in a
sample period will stop data transmission because TXS
or RXS will never equal the PCLK count. Figures 29–32
illustrate the usage of the PCM highway interface to
adapt to common PCM standards.
LSB
LSB
8
8
LSB
LSB
9
9
10
10
11
11
12
12
HI-Z
HI-Z
13
13
14
14
Si3210/Si3211
15
15
16
16
17
17
18
18
55