SI4313-B1-FMR Silicon Laboratories Inc, SI4313-B1-FMR Datasheet - Page 17

• Manufacturer Part Number: SI4313-B1-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4313-B1-FMR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3. Controller Interface
3.1. Serial Peripheral Interface
The Si4313 communicates with the host MCU over a standard three-wire SPI interface: SCLK, SDI, and nSEL. The
host MCU can read data from the device on the SDO output pin. An SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit followed by a 7-bit address field (ADDR) and an 8-bit data field (DATA).
The 7-bit address field supports reading from or writing to one of the 128 8-bit control registers. The R/W select bit
determines whether the SPI transaction is a read or write transaction. If R/W = 1, it signifies a WRITE transaction,
while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the Si4313 every eight
clock cycles. Timing parameters are shown in Table 9. The SCLK rate is flexible with a maximum rate of 10 MHz.
To read back data from the Si4313, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R/W = 0. The next
eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read
from the selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After
the READ function is completed, the SDO pin will remain at either a logic 1 or logic 0 state depending on the last
data bit clocked out (D0). When nSEL goes high, the SDO output pin will be pulled high by internal pull-up.
Symbol
t
t
t
t
t
t
t
t
t
t
SW
CH
DS
DH
DD
EN
DE
SH
CL
SS
SCLK
nSEL
Output data delay time
Output disable time
Output enable time
Select high period
Select setup time
SDI
Select hold time
Data setup time
Clock high time
Clock low time
Data hold time
Parameter
MSB
RW
A6 A5
Table 9. Serial Interface Timing Parameters
Min (nsec)
A4
Address
50
80
40
40
20
20
20
20
50
20
A3
Figure 2. SPI Timing
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Rev. 1.0
SDI
SCLK
SDO
nSEL
t
t
EN
SS
Data
t
CL
t
CH
Diagram
t
DS
t
DH
LSB
t
DD
Si4313-B1
xx xx
t
SH
RW A7
t
DE
t
SW
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