SI4313-B1-FMR Silicon Laboratories Inc, SI4313-B1-FMR Datasheet - Page 32

• Manufacturer Part Number: SI4313-B1-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4313-B1-FMR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Si4313-B1
8. Auxiliary Functions
8.1. Smart Reset
The Si4313 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector, POR. This reset circuit was designed to produce a reliable
reset signal under any circumstances. Reset will be initiated if any of the following conditions occurs:




The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
32
Initial power on, VDD starts from GND: reset is active till VDD reaches VRR (see table).
When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR.
A software reset via Register 08h. "Operating Mode and Function Control 2," where reset is active for time
On the rising edge of a VDD glitch when the supply voltage exceeds the time functioned limit of Figure 10.
VDD Glitch Reset Pulse
TSWRST.
Release Reset Voltage
Power-On VDD Slope
Software Reset Pulse
Threshold Voltage
Reference Slope
Low VDD Limit
Parameter
0.4V
VDD starts to rise
Symbol
T
SVDD
VTSD
SWRST
VRR
VLD
TP
K
Figure 10. POR Glitch Parameters
VDD(t)
Table 13. POR Parameters
t=0,
Also occurs after SDN, and initial
VDD nom.
Tested VDD Slope Region
Rev. 1.0
VLD<VRR
Comment
power on
reset:
Vglitch>=0.4+t*0.2V/ms
showing glitch
actual VDD(t)
Reset
0.4V+t*0.2V/ms
T
P
reset limit:
t
0.85
0.03
Min
0.7
50
5
Typ
0.4
1.3
0.2
16
1
Max
1.75
300
470
1.3
40
V/ms
V/ms
Unit
ms
µs
V
V
V