SI4313-B1-FMR Silicon Laboratories Inc, SI4313-B1-FMR Datasheet - Page 22

• Manufacturer Part Number: SI4313-B1-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4313-B1-FMR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Si4313-B1
3.4. System Timing
The VCO will automatically calibrate at every frequency change or power-up. The PLL T0 time is to allow for bias
settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The
total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. In certain applications, the PLL T0 time
and the PLL CAL may be skipped for faster turnaround time. Contact applications support if faster turnaround time
is desired.
3.5. Frequency Control
To calculate the necessary frequency register settings, use the Silicon Labs' Wireless Design Suite (WDS) or Excel
Calculator available from the product web page. These methods offer a simple, quick interface to determine the
correct settings based on the application requirement.
3.5.1. Automatic State Transition for Frequency Change
If registers 79h or 7Ah are changed in RX mode, the state machine will automatically transition the chip back to
tune and change the frequency. This feature is useful to reduce the number of SPI commands required in a
Frequency Hopping System. In turn, this reduces microcontroller activity, thereby reducing current consumption.
3.5.2. Frequency Offset Adjustment
When the AFC is disabled, the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The
frequency offset adjustment and the AFC are both implemented by shifting the Synthesizer Local Oscillator
frequency. This register is a signed register; so, in order to get a negative offset, it is necessary to take the twos
22
Add
75
76
77
R/W
R/W
R/W
R/W
Frequency Band Select
Nominal Carrier Fre-
Nominal Carrier Fre-
Function/Description
quency 1
quency 0
fc[15]
fc[7]
D7
Figure 7. RX Timing
fc[14]
sbsel
fc[6]
D6
Rev. 1.0
hbsel
fc[13]
fc[5]
D5
fc[12]
fb[4]
fc[4]
D4
Data
fc[11]
fb[3]
fc[3]
D3
fc[10]
fb[2]
fc[2]
D2
fb[1]
fc[9]
fc[1]
D1
fb[0]
fc[8]
fc[0]
D0
Default
POR
BBh
35h
80h