DS2180AN Maxim Integrated Products, DS2180AN Datasheet - Page 4

• Manufacturer Part Number: DS2180AN
• Description: IC TRANSCEIVER T1 IND 40-DIP
• Manufacturer: Maxim Integrated Products

Specifications of DS2180AN

• Function: Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 3mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Includes: Alarm Generation and Detection, B7 Stuffing Mode, B8ZS Mode, Error Detection and Counter, "Hardware" Mode, Transparent Mode
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN
PIN
20
32
40
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
SYMBOL
SYMBOL
RMSYNC
RCHCLK
RSIGSEL
RFSYNC
RABCD
RSIGFR
RLCLK
RLINK
RNEG
RYEL
RCLK
RSER
RPOS
RFER
RLOS
TEST
RBV
RCL
RST
V
V
DD
SS
TYPE
TYPE
O
O
O
O
O
O
O
O
O
O
O
0
0
0
-
I
-
I
I
I
Signal Ground. 0.0 volts.
Test Mode. Tie to V
Positive Supply. 5.0 volts.
Receive Yellow Alarm. Transitions high when yellow alarm detected, goes low
when alarm clears.
Receive Link Data. Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
Receive Link Clock. 4 kHz demand clock for RLINK.
Receive Clock. 1.544 MHz primary clock.
Receive Channel Clock. 192 kHz clock identifies time slot (channel) boundaries.
Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK.
Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
Receive Multiframe Sync. Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
Receive ABCD Signaling. Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
Receive Signaling Frame. High during signaling frames, low during resync and
non-signaling frames.
Receive Signaling Select. In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
Reset. A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
Receive Bipolar Data Inputs. Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
Receive Carrier Loss. High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
Receive Bipolar Violation. High during accused bit time at RSER if bipolar
violation detected, low otherwise.
Receive Frame Error. High during F-Bit time when F
or when FPS or CRC errors occur (193E). Low during resync.
Receive Loss of Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
4 of 35
SS
for normal operation.
DESCRIPTION
DESCRIPTION
T
or F
S
errors occur (193S)
DS2180A