PEB 20570 F V3.1 Infineon Technologies, PEB 20570 F V3.1 Datasheet - Page 100

• Manufacturer Part Number: PEB 20570 F V3.1
• Description: IC LINE CARD CTRLR HDLC TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEB 20570 F V3.1

• Function: Line Card Controller
• Interface: ISDN
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 272.6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20570FV3.1X; PEB20570FV31XP; SP000007243

4.2.9
The S/T interface establishes a direct link between the VIP and connected subscriber
terminals or to the Central Office. It consists of two pairs of copper wires: one for the
transmit and one for the receive direction.
Direct access to the VIP’s S/T interface by the DELIC is not possible. 2B+D user data as
well as S/Q channel information can be inserted and extracted via the IOM-2000
interface.
Framing bits are generated and transmitted to the VIP by the DELIC.
Transmission over the S/T interface is performed at a rate of 192 kbit/s. Pseudo-ternary
coding with 100 % pulse width is used. 144 kbit/s are used for user data (36 bits of
B1+B2+D) and 48 kbit/s (12 bits) are used for framing, S/Q and maintenance
information. For each S/T channel, the VIP uses two symmetrical, differential outputs
(SX1, SX2) and two symmetrical, differential inputs (SR1, SR2). These signals are
coupled via external circuitry and two transformers onto the 4 wire S/T interface. The
nominal pulse amplitude on the S/T interface is 750 mV (zero-peak).
S/T Coding
The following figure illustrates the code used. A binary ONE is represented by no line
signal (0 V). Binary ZEROs are coded with alternating positive and negative pulses with
two exceptions: the first binary ZERO following the framing balance bit is of the same
polarity as the framing-balancing bit, and the F-bit is always at positive level (required
code violations).
Figure 25
A standard S/T frame consists of 48 bits. In the direction TE
transmitted with a 2-bit offset. For details on the framing rules please refer to ITU I.430.
The following figure illustrates the standard frame structure for both directions (NT
and TE
Data Sheet
NT) with all framing and maintenance bits.
S/T Interface Frame Structure
S/T Interface Line Code (without code violation)
83
Functional Description
NT the frame is
PEB 20570
PEB 20571
2003-07-31
TE