PEB 20570 F V3.1 Infineon Technologies, PEB 20570 F V3.1 Datasheet - Page 106

• Manufacturer Part Number: PEB 20570 F V3.1
• Description: IC LINE CARD CTRLR HDLC TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEB 20570 F V3.1

• Function: Line Card Controller
• Interface: ISDN
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 272.6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20570FV3.1X; PEB20570FV31XP; SP000007243

• The B-channel data is prepared by the DSP in the Data RAM and inserted into the
• If collision was detected on the D-channel, the data transmission on this channel is
• The B- and D-channel data bits and F
Collision Detection on D-channel in LT-T Mode
The collision is detected on the D-channel when the received E-bit is not equal to the last
transmitted D-bit.
• The TRANSIU compares the E-bit with the D-bit
• When the collision is detected, the TRANSIU indicates collision to the DSP, and starts
• The priority mechanism is implemented in software. The TRANSIU provides the
• The DSP counts to 8/9 (higher priority) or 10/11 (lower priority) and enables the
• If the new collision was detected by the TRANSIU during the current collision, the DSP
Data Sheet
downstream frame by the TRANSIU
blocked by the TRANSIU and the 1’s are sent on the D-channel instead of the data
from the Data RAM until the data sending is enabled by the DSP
in the same format as LT-S received frames
to send 1’s on the D-channel.
following information to the DSP (2 bits per LT-T – configured channel, which are
stored in the Data RAM, see
TRANSIU to transmit the data on the D-channel at the end of counting. The TRANSIU
stops D-channel blocking immediately, all relevant data (end of Idle or start of the flag)
is already prepared by the DSP in the Data RAM.
resets the priority mechanism counters and starts counting from the beginning.
–Collision detection on D-channel (Cl-bit): ‘0’ – no collision in the D-channel,
–Collision detection bit number: ‘0’ – collision was detected in the 1-st bit of the
‘1’ – collision was detected in the D-channel.
frame, ‘1’ – collision was detected in the 2-nd bit of the frame.
“LT-T Mode Receive Data Format” on Page
a
-bit are prepared by the DSP in the Data RAM
89
Functional Description
PEB 20570
PEB 20571
2003-07-31
94.