PEB 20570 F V3.1 Infineon Technologies, PEB 20570 F V3.1 Datasheet - Page 22

• Manufacturer Part Number: PEB 20570 F V3.1
• Description: IC LINE CARD CTRLR HDLC TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEB 20570 F V3.1

• Function: Line Card Controller
• Interface: ISDN
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 272.6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20570FV3.1X; PEB20570FV31XP; SP000007243

List of maximum available features:
• One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels
• Support of DASL mode
• Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16
• Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or
• Switching matrix 256 x 256 TS (switching of 4-/8- bit time slots)
• Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Up to 4 serial communication controllers: one of them with up to 8.192 Mbit/s data rate
• General purpose I/O ports
• DECT synchronization support
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Dedicated DMA support mailbox for 2 DMA-channels
• Integrated DSP core OAK+ (60 MIPS for layer 1 control, signalling and DSP-
• 4 kWord on-chip program memory
• 2 kWord on-chip data memory
• 2 kWord ROM
• DSP work load measurement for run-time statistics, DSP alive indication
• On chip debugging unit
• Serial DSP program debugging interface connected via JTAG port
• A-/µ-law conversion unit
• Programmable PLL based Master/Slave clock generator, providing all system clocks
• JTAG compliant test interface
• single 3.3 V power supply, 5 V compatible inputs
Note: As each feature consumes system resources (DSP-MIPS, memory, port pins), the
Data Sheet
ISDN channels or 32 analog subscribers
1 x 8.192 Mbit/s
algorithms)
from a single 16.384 MHz crystal source
maximum available number of supported interfaces or HDLC channels is limited
by the totally available resources. A System Configurator tool (see DELIC
Software User’s Manual) helps to determine a valid configuration.
5
Introduction
PEB 20570
PEB 20571
2003-07-31