PEB 20954 HT V1.1 Infineon Technologies, PEB 20954 HT V1.1 Datasheet - Page 34

• Manufacturer Part Number: PEB 20954 HT V1.1
• Description: IC SIDEC T/E 32CHAN TQFP-144-8
• Manufacturer: Infineon Technologies

Specifications of PEB 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 4
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection, Maskable Disabling, Voiceband Echo Cancelling
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEB20954HTV1.1T; PEB20954HTV11XP; SP000007504; SP000007506

Table 16
Ball No. Symbol
E14
F13
B14
C14
D13
Table 17
Ball No. Symbol
M14
N14
P14
P13
N5,P4,
N4,P3,
N3,P2N
2
P9,N8,P
8,P7,N7
,P6,N6,
P5
Data Sheet
RFCLKEX
CLK16
CTRL16
RFSPF
RFSPN
IM0
IM1
CS0
CS1
A0..A6
AD0..AD7
Synchronization (cont’d)
Microprocessor Interface
I/O, PU/PD Function
I/O, PU/PD Function
I, PU
I, PU
O
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I/O, -
Reference clock (2.048 MHz) for frequency
comparison to generate the control voltage for
the 16.384 MHz VCXO if Register
FSLIPIV[6]='1'
Clock from 16.384 MHz VCXO
Control voltage for the 16.384 MHz VCXO
Receive Frame Sync Pulse from the far end
side (F1). This pulse of 488 ns width marks
timeslot 0 when writing into Elastic Store (e.g.
FALC) to prevent faults in one frame length
mode. To use this pin Register FSLIPIV[5]
must be '0'.
Receive Frame Sync Pulse from the near end
side (F2). This pulse of 488 ns width marks
timeslot 0 when writing into Elastic Store (e.g.
FALC) to prevent faults in one frame length
mode. To use this pin Register FSLIPIV[5]
must be '1'.
Interface Mode Intel = low, Motorola = high
Interface Mode MUXED = low, DEMUXED =
high
Chip Select. A low signal selects the SIDEC
(internally "anded" with CS1).
Chip Select. A low signal selects the SIDEC
(internally "anded" with CS0).
Address Bus. Only used in demuxed mode,
can be left open in muxed mode.
Multiplexed Address/Data Bus in multiplexed
mode, Data Bus in demultiplexed mode
34
Rev. 2, 2004-07-28
Pin Description
PEB 20954
PEF 20954