PEB 20954 HT V1.1 Infineon Technologies, PEB 20954 HT V1.1 Datasheet - Page 52

• Manufacturer Part Number: PEB 20954 HT V1.1
• Description: IC SIDEC T/E 32CHAN TQFP-144-8
• Manufacturer: Infineon Technologies

Specifications of PEB 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 4
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection, Maskable Disabling, Voiceband Echo Cancelling
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEB20954HTV1.1T; PEB20954HTV11XP; SP000007504; SP000007506

4.2
The SIDEC can be connected in different synchronization and clock modes. These
modes can be used for several applications.
Basically there are two clock modes, slave and master clock mode (not to be mixed up
with 128 ms master and slave mode). The internal clock system in master clock mode is
automatically synchronized to the system clock by using an external 32.768 MHz VCO
or by generating and deriving the system clock at output pin SCLKO directly from the
CLK32 input. SIDEC in master clock mode provides a synchronization pulse at pin
SDECO. This pulse can be used by a SIDEC in slave clock mode to synchronize its
internal clock system to the system clock without the needs for additional external VCO.
Examples for this mode are the 128 ms delay application and the multiple SIDEC
application, see also
CLK4O is 4.096 MHz system clock output for subsequent circuits, derived from SCLKI.
Figure 13
In
process the PCM signals. The system clock at pin SCLKO can also be provided for other
devices. The SDECI pin is not connected in the master clock mode. A 32.768 MHz clock
has to be provided by an external clock oscillator or other clock source on the system.
Data Sheet
Figure 13
Synchronization and Clock Modes
SCLKO
SDECI n.c.
8.192MHz
the system clock is reconnected from SCLKO to SCLKI in order to properly
Master Clock Mode, ext. 32.768 MHz, no SDECI Clock
SCLKI
Figure 17
SIDEC
and
Figure
52
Master Clock Mode 32MHz wo 8MHz
18.
SDECO (to slave)
CLK4O
Operational Description
Rev. 2, 2004-07-28
PEB 20954
PEF 20954