PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 135

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

For DCL = 1.536 MHz one of the IOM-2 channels 0 - 2 can be selected, for DCL =
4.096 MHz any of the eight IOM-2 channels can be selected.
The channel select pins have direct effect on the timeslot selection of the following
registers:
• TR_TSDP_BC1
• TR_TSDP_BC2
• TR_CR, TRC_CR
• DCI_CR, DCIC_CR
• MON_CR
HDLC Controllers
The ISAC-SX contains two HDLC controllers. The first one is used for the layer-2
functions of the D- channel protocol (LAPD), the second one provides B-channel access
with reduced FIFO thresholds which can be used for firmware upgrade via the line for
example. By setting the Enable HDLC channel bits (EN_D, EN_B1H) in the DCI_CR/
BCH_CR registers each of the HDLC controllers can access the D or B-channels on
IOM-2.
They perform the framing functions used in HDLC based communication: flag
generation/recognition, bit stuffing, CRC check and address recognition.
The FIFO has a size of 64 byte per direction for the D-channel and 128 byte per direction
for the B-channel. They are implemented as cyclic buffers. The transceiver reads and
writes data sequentially with constant data rate whereas the data transfer between FIFO
and microcontroller uses a block oriented protocol with variable block sizes.
The configuration, control and status bits related to the HDLC controllers are all assigned
to the following address ranges:
Table 17
D-channel
B-channel
Note: For B-channel data access a single address location is used to read from and write
The mechanisms for access to the FIFOs are identical for D- and B-channels, therefore
the following description applies to both of them and for simplification specific references
Data Sheet
to the FIFO. For D-channel access the address range 00
in ISAC-S PEB 2086), however a single address from this range is sufficient to
access the FIFO as the internal FIFO pointer is incremented automatically
independent from the external address.
HDLC Controller Address Range
FIFO Address
00
7A
H
H
-1F
H
135
Description of Functional Blocks
Config/Ctrl/Status Registers
20
70
H
H
-29
-79
H
H
H
-1F
H
is used (similar as
PEB 3086
2003-01-30
ISAC-SX