PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 32

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

3.2
The ISAC-SX supports a serial or a parallel microcontroller interface. For applications
where no controller is connected to the ISAC-SX microcontroller interface programming
is done via the IOM-2 MONITOR channel from a master device. In such applications the
ISAC-SX operates in the IOM-2 slave mode (refer to the corresponding chapter of the
IOM-2 MONITOR handler). This mode is suitable for control functions (e.g. programming
registers of the S/T transceiver), but the bandwidth is not sufficient for access to the
HDLC controllers.
The interface selections are all done by pinstrapping (see
are evaluated when the reset input RES is active. For the pin levels stated in the tables
the following is defined:
’High’, ’Low’: dynamic pin; value must be ’High’ or ’Low’ only during reset
V
edge:
Table 3
WR
(R/W)
’High’
V
Note: For a selected interface mode which doesn’t need all input selection and address
The interfaces contain all circuitry necessary for the access to programmable registers,
status registers and HDLC FIFOs. The mapping of all these registers can be found in
Chapter
The microcontroller interface also provides an interrupt request at pin INT which is low
active by default but can be reprogrammed to high active, a reset input pin RES and a
reset output pin RSTO.
The interrupt request pin INT becomes active if the ISAC-SX requests an interrupt and
this can occur at any time.
Data Sheet
DD
SS
, V
PINS
pins the unused pins must be tied to V
SS
RD
(DS)
’High’ Parallel
V
4.
:
SS
Microcontroller Interfaces
static pin; pin must statically be strapped to ’High’ or ’Low’ level
dynamic pin; any transition (’High’ to ’Low’, ’Low’ to ’High’) has occured
Host Interface Selection
Serial /Parallel
Interface
Serial
No
Host Interface
CS
‘High’ V
’High’ V
V
SS
PINS
ALE
V
edge
V
DD
SS
SS
SS
32
DD
or V
Interface
Type/Mode
Motorola
Siemens/Intel Non-Mux
Siemens/Intel Mux
Serial Control Interface(SCI)
IOM-2 MONITOR Channel
(Slave Mode)
Description of Functional Blocks
SS
.
Table
3). The selection pins
PEB 3086
2003-01-30
ISAC-SX