SC16C852LIBS,151 NXP Semiconductors, SC16C852LIBS,151 Datasheet - Page 35

• Manufacturer Part Number: SC16C852LIBS,151
• Description: IC UART DUAL W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 485r

Specifications of SC16C852LIBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 1.95 V
• Supply Voltage (min): 1.65 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V
• Transmitter And Receiver Fifo Counter: Yes
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4209; 935283101151; SC16C852LIBS-S

NXP Semiconductors
SC16C852L
Product data sheet
7.10 Scratchpad Register (SPR)
7.12 Transmit FIFO Level Count (TXLVLCNT)
7.13 Receive FIFO Level Count (RXLVLCNT)
7.11 Division Latch (DLL and DLM)
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers: first extra
feature register set, second extra feature register set, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 24.
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
The SC16C852L provides a temporary data register to store 8 bits of user information.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores
the least significant part of the division.
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RX FIFO).
Bit
7:3
2:1
0
Symbol
EFCR[7:3]
EFCR[2:1]
EFCR[0]
Extra Feature Control Register bits description
All information provided in this document is subject to legal disclaimers.
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 4 — 1 February 2011
Description
reserved
Enable Extra Feature Control bits
Enable TXLVLCNT and RXLVLCNT access
00 = General register set is accessible
01 = First extra feature register set is accessible
10 = Second extra feature register set is accessible
11 = reserved
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read.
SC16C852L
© NXP B.V. 2011. All rights reserved.
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