SC16C754BIBM,151 NXP Semiconductors, SC16C754BIBM,151 Datasheet - Page 19

• Manufacturer Part Number: SC16C754BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIBM,151

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3290; 935279069151; SC16C754BIBM-S

NXP Semiconductors
SC16C754B_4
Product data sheet
6.8 Break and time-out conditions
6.9 Programmable baud rate generator
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
The SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure
formula for the divisor is given in
Where:
Remark: The default value of prescaler after reset is divide-by-1.
Figure 13
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least significant and most significant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7
1.8432 MHz and 3.072 MHz, respectively.
Figure 14
divisor
Fig 13. Prescaler and baud rate generator block diagram
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
XTAL1
XTAL2
13. The output frequency of the baud rate generator is 16
and
=
shows the internal prescaler and baud rate generator circuitry.
shows the crystal clock circuit reference.
----------------------------------------------------------------------------------------- -
XTAL1 crystal input frequency
------------------------------------------------------------------------------------ -
Table 8
OSCILLATOR
INTERNAL
desired baud rate
LOGIC
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
show the baud rate and divisor correlation for crystal with frequency
Rev. 04 — 6 October 2008
prescaler
input clock
Equation
(DIVIDE-BY-1)
(DIVIDE-BY-4)
PRESCALER
PRESCALER
16
LOGIC
LOGIC
1:
MCR[7] = 0
MCR[7] = 1
reference
clock
16
GENERATOR
BAUD RATE
LOGIC
SC16C754B
1). An additional
the baud rate. The
© NXP B.V. 2008. All rights reserved.
002aaa233
internal
baud rate
clock for
transmitter
and receiver
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