SC16C754BIBM,151 NXP Semiconductors, SC16C754BIBM,151 Datasheet - Page 31

• Manufacturer Part Number: SC16C754BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIBM,151

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3290; 935279069151; SC16C754BIBM-S

NXP Semiconductors
SC16C754B_4
Product data sheet
7.10 Enhanced Feature Register (EFR)
7.11 Divisor latches (DLL, DLM)
This 8-bit register enables or disables the enhanced features of the UART.
the enhanced feature register bit settings.
Table 19.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLM can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced feature register bits description
Description
CTS flow control enable.
RTS flow control enable.
Special character detect.
Enhanced functions enable bit.
Combinations of software flow control can be selected by programming these
bits. See
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logic 1 to indicate a special character has been detected.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
can be modified, that is, this bit is therefore a write enable.
Rev. 04 — 6 October 2008
Table 3 “Software flow control options
(EFR[3:0])”.
SC16C754B
© NXP B.V. 2008. All rights reserved.
Table 19
shows
31 of 51