SC16C654BIA68,512 NXP Semiconductors, SC16C654BIA68,512 Datasheet - Page 26

• Manufacturer Part Number: SC16C654BIA68,512
• Description: ID QUAD UART 64BYTE 68PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIA68,512

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274935512; SC16C654BIA68; SC16C654BIA68

Philips Semiconductors
9397 750 14965
Product data sheet
7.2.1 IER versus Receive FIFO interrupt mode operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
Table 9:
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
Bit
2
1
0
•
•
•
•
•
•
•
•
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be cleared
when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
Symbol
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Description
Receive Line Status interrupt.
Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
Rev. 02 — 20 June 2005
SC16C654B/654DB
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
26 of 58