SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 32

• Manufacturer Part Number: SC28L92A1B,557
• Description: IC UART DUAL W/FIFO 44-PQFP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr
• Type: Dual UARTr

Specifications of SC28L92A1B,557

• Number Of Channels: 2, DUART
• Package / Case: 44-MQFP, 44-PQFP
• Features: False-start Bit Detection
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.2304 MBd
• Supply Voltage (max): 3.63 V or 5.5 V
• Supply Voltage (min): 2.97 V or 4.5 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1211; 935263294557; SC28L92A1B

NXP Semiconductors
SC28L92_7
Product data sheet
7.3.1.4 Mode Register 0 channel B (MR0B)
7.3.1.5 Mode Register 1 channel B (MR1B)
7.3.1.6 Mode Register 2 channel B (MR2B)
Table 32.
[1]
MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The
pointer is set to MR0 by RESET or by a set pointer command applied via CRB. After
reading or writing MR0B, the pointer will point to MR1B.
The bit definitions for this register are identical to MR0A, except the FIFO size bit and that
all control actions apply to the channel B receiver, transmitter, the corresponding inputs
and outputs. MR0B[2:0] are reserved.
MR1B (address 0x8) is accessed when the channel B MR pointer points to MR1. The
pointer is set to MR1 by RESET or by a set pointer command applied via CRB. After
reading or writing MR1B, the pointer will point to MR2B.
The bit definitions for this register are identical to MR1A, except that all control actions
apply to the channel B receiver and transmitter and the corresponding inputs and outputs.
MR2B (address 0x8) is accessed when the channel B MR pointer points to MR2, which
occurs after any access to MR1B. Accesses to MR2B do not change the pointer.
The bit definitions for mode register are identical to the bit definitions for MR2A, except
that all control actions apply to the channel B receiver and transmitter and the
corresponding inputs and outputs.
MR2A[3:0] (hexadecimal)
B
C
D
E
F
Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character
Stop bit length
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
…continued
Stop bit length
1.750
1.813
1.875
1.938
2.000
[1]
SC28L92
© NXP B.V. 2007. All rights reserved.
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