SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 36

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
Fig 18. Master writes to slave
Fig 19. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS741
Grey block: SC16IS741 to host
White block: host to SC16IS741
Grey block: SC16IS741 to host
SLAVE ADDRESS
Table 29
Table 29
S
for additional information.
for additional information.
SLAVE ADDRESS
Table 29
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I
SPI interface to indicate a read or a write operation.
The register read cycle (see
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated
START followed again by the device address, but this time with the direction bit set to
‘read’. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.
Table 29.
Bit
7
6:3
2:1
0
W
and
Register address byte (I
Name
-
A[3:0]
CH1, CH0
-
Table 30
A
W
REGISTER ADDRESS
Single UART with I
show the bits’ presentation at the subaddress byte for I
Rev. 01 — 29 April 2010
A
REGISTER ADDRESS
Figure
Function
not used
UART’s internal register select
channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
not used
2
(1)
C)
19) commences in a similar manner, with the master
A
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
nDATA
(1)
S
A
2
SLAVE ADDRESS
C-bus interface, but it is used by the
A
nDATA
LAST DATA
A
SC16IS741
002aab047
R
© NXP B.V. 2010. All rights reserved.
P
NA
A
2
002aab048
C-bus and
P
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