SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 7

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
Fig 5.
Fig 6.
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the current
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
RTS functional timing
character, but it does not send the next character.
CTS functional timing
receive
FIFO
RTS
read
RX
7.2.1 Auto RTS
7.2.2 Auto CTS
CTS
TX
Figure 5
are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger
level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
The sending device (for example, another UART) may send an additional character after
the trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
start
Figure 6
sending the next data byte. When CTS is active, the transmitter sends the next byte. To
stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto CTS function reduces
interrupts to the host system. When flow control is enabled, CTS level changes do not
trigger host interrupts because the device automatically controls its own transmitter.
Without auto CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
character
shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS
shows CTS functional timing. The transmitter circuitry checks CTS before
N
start
stop
bit 0 to bit 7
Single UART with I
Rev. 01 — 29 April 2010
start
stop
character
N + 1
1
2
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
stop
start
bit 0 to bit 7
N
N + 1
SC16IS741
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Section 7.2.1
stop
© NXP B.V. 2010. All rights reserved.
002aab040
start
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