SC16C852SVIET,157 NXP Semiconductors, SC16C852SVIET,157 Datasheet - Page 12

• Manufacturer Part Number: SC16C852SVIET,157
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451157; SC16C852SVIET; SC16C852SVIET

NXP Semiconductors
SC16C852SV_1
Product data sheet
6.9 Programmable baud rate generator
The SC16C852SV UART contains a programmable rational baud rate generator that
takes any clock input and divides it by a divisor in the range between 1 and (2
SC16C852SV offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the First Extra
Register Set.
where:
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
Remark:
A single baud rate generator is provided for the transmitter and receiver. The
programmable baud rate generator is capable of operating with a frequency of up to
80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C852SV can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see
to the XTAL1 pin (see
custom rates (see
The generator divides the input 16 clock by any divisor from 1 to (2
SC16C852SV divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
baud rate
Fig 4.
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
f
SAMPR is the sampling rate in SAMPR register (16 , 8 , 4 )
XTAL1
XTAL1
XTAL2
is the clock frequency at XTAL1 pin;
Prescalers and baud rate generator block diagram
------------------- -
SAMPR
=
OSCILLATOR
M
------------------------------------------------------------------------------------------------ -
MCR 7
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table
should always be less than 1.
Rev. 01 — 23 September 2008
Figure
6).
SAMPR
Figure
f
DIVIDE-BY-1
DIVIDE-BY-4
6) to clock the internal baud rate generator for standard or
XTAL1
5). Alternatively, an external clock can be connected
N
+
------------------- -
SAMPR
MCR[7] = 0
MCR[7] = 1
M
GENERATOR
BAUD RATE
SC16C852SV
(DLL, DLM)
CLKPRES
[3:0]
16
© NXP B.V. 2008. All rights reserved.
1). The
transmitter and
receiver clock
16
002aac645
1). The
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