SC16C852SVIET,157 NXP Semiconductors, SC16C852SVIET,157 Datasheet - Page 33
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SC16C852SVIET,157
Manufacturer Part Number
SC16C852SVIET,157
Description
IC UART DL 1.8V W/FIFO 36-TFBGA
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C852SVIET151.pdf
(48 pages)
Specifications of SC16C852SVIET,157
Features
Programmable
Number Of Channels
2, DUART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
1.8V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
36-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286451157
SC16C852SVIET
SC16C852SVIET
SC16C852SVIET
SC16C852SVIET
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C852SVIET,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C852SV_1
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 27.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 28.
[1]
This register hold values for the clock prescaler.
Table 29.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Symbol
FLWCNTH[7:0]
Symbol
FLWCNTL[7:0]
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 01 — 23 September 2008
Section
Section
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.
Description
reserved
clock prescaler value; reset to 0
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section 7.3 “FIFO Control Register
Section 7.3 “FIFO Control Register
6.5.
6.5.
Table 27
Table 28
(FCR)”.
(FCR)”.
SC16C852SV
shows transmission control
shows transmission control
© NXP B.V. 2008. All rights reserved.
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