TDA8933BTW/N2,118 NXP Semiconductors, TDA8933BTW/N2,118 Datasheet - Page 11

• Manufacturer Part Number: TDA8933BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8933BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 20.6W x 1 @ 16 Ohm; 10.3W x 2 @ 8 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285222118

NXP Semiconductors
UBA2074(A)
Preliminary data sheet
7.7 PWM dimming
During the time within a PWM dim cycle that the lamps are off, switches S1 and S2 are
opened (non-conducting). In this way the regulation level is stored in C1 when the current
regulation loop is opened (see
After the regulation loop is opened, C2 is discharged (the voltage on the CSWP-pin is
swept down) to switch off the lamps, and charged again to turn the lamps on again. The
lamps on versus off time is determined by the signal on the PWMd-pin (low = lamps on).
each PWM cycle is ∆φ
configuration. ∆φ
zero voltage switching at high bridge voltages.
During the PWM lamps off period the phase shift level at which the lamp current was in
regulation is preserved in the capacitor connected to the CIFB-pin (C1 in
Switches S1 and S2 are closed (conducting) again when the voltage on the CSWP-pin
has reached the voltage on the CIFB-pin again.
The phase shift sweep speed is determined by the capacitor connected to the CSWP-pin
(C2 in
cycle because of the phase shift sweep time (see
too short to sweep up the voltage on the CSWP-pin, the IC will wait until the CSWP
voltage has actually reached the current control level before sweeping down again. This
prevents that the lamps go out completely when deep dimming is combined with a too
large capacitor at the CSWP-pin.
Three pins are available to configure the internal PWM generator: the CPWM-, PWMa-,
and the PWMD-pin. The two possible PWM configurations are shown in
analog or master mode the internal PWM generator is active and generating the PWM
signal. This signal is put on the PWMd-pin, which is automatically configured as an output.
The minimum dutycycle of the internal PWM generator is limited to D
When the CPWM-pin is connected to ground, the IC is put in digital or slave mode. The
PWMd-pin is then an input and the IC uses the PWM signal provided on the PWMd-pin.
The minimum phase difference between the bridge halves during the lamps off period of
Fig 10. Light output as function of PWMa input voltage
Figure
9). The real lamp light output will be slightly less then the PWMd signal duty
(min,hv)
Rev. 02.0 — February 2007
(min,lv)
>∆φ
(min,lv)
High Voltage Full-bridge control IC for CCFL backlighting
in low voltage configuration and ∆φ
Figure
because of the need to keep commuttation current for
9).
Figure
10). When the lamp-on time is
(min,hv)
UBA2074(A)
PWM(min,intern)
in high voltage
© NXP B.V. 2007. All rights reserved.
Figure
Figure
11. In the
9).
.
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