S3006 AMCC (Applied Micro Circuits Corp), S3006 Datasheet

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S3006

Manufacturer Part Number
S3006
Description
SONET / SDH OC-3/12 Transmitter and Receiver
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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FEATURES
APPLICATIONS
Figure 1. System Block Diagram
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
DEVICE SPECIFICATION
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
• Complies with ANSI, Bellcore, and ITU-T
• On-chip high-frequency PLL for clock
• Supports 139.264 Mbit/s (E4), 155.52 Mbit/s
• Supports 139.264 Mbit/s and 155.52 Mbit/s
• Selectable reference frequencies of 19.44,
• Interface to both ECL and TTL logic
• 8-bit TTL/CMOS datapath
• Bypass mode for off-chip clocking
• Local and line loopback mode
• Lock detect
• Low jitter ECL interface
• Low power
• 80 PQFP or 68 LDCC package
• SONET/SDH or E4-based transmission systems
• SONET/SDH or E4 modules
• SONET/SDH or E4 test equipment
• ATM over SONET
• Section repeaters
• Add drop multiplexors
• Broadband cross-connects
• Fiber optic terminators
• Fiber optic test equipment
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
Processor
Overhead
specifications
generation and clock recovery
(OC-3), and 622.08 Mbit/s (OC-12)
transmission rates
Code Mark Inversion (CMI) interfaces
38.88, 51.84, and 77.76 MHz (OC-3/12) and
17.408, 34.816, 46.421, and 69.632 MHz(E4)
Transmit
8
SONET/SDH
Transmitter
S3005
(SETI)
OTX
GENERAL DESCRIPTION
The S3005/S3006 Synchronous Electrical Transmit
Interface, SETI, and Synchronous Electrical Receive
Interface, SERI, SONET/SDH and E4 transmitter
and receiver chips are the first fully integrated serial-
ization/deserialization interface devices covering E4
(139.264 Mbit/s), SONET OC-3 (155.52 Mbit/s) and
SONET OC-12 (622.08 Mbit/s). With architecture de-
veloped by PMC-Sierra, the chipset performs all
necessary serial-to-parallel and parallel-to-serial
functions in conformance with SONET/SDH and E4
transmissions standards. Figure 1 shows a typical
network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3005 SETI
transmitter chip allowing the use of a slower external
transmit clock reference.
formed on the S3006 SERI receiver chip by
synchronizing its on-chip VCO directly to the incom-
ing data stream. The S3006 also performs SONET/
SDH frame detection. The chipset can be used with
19.44, 38.88, 51.84, and 77.76 MHz reference
clocks when operated in the SONET/SDH OC-3 or
OC-12 modes. In the E4 mode the chipset can be
operated with 17.408, 34.816, and 69.632 MHz ref-
erence clocks in support of existing system clocking
schemes. On-chip code-mark-inversion (CMI) encod-
ing and decoding is provided for 139.264 Mbit/s and
155.52 Mbit/s interfaces. If desired, both clock gen-
eration and recovery can be bypassed, allowing the
use of externally generated and recovered clocks.
The very low jitter ECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore, ANSI, and ITU-T standards. The S3005/
S3006 SETI and SERI chipset is packaged in a 50
mil pitch, 68-pin LDCC or 25 mil pitch, 80 PQFP
package, offering designers a small package outline.
ORX
SONET/SDH
Receiver
(SERI)
S3006
Clock recovery is per-
8
S3005/S3006
S3005/S3006
Processor
Overhead
Receive
®
1

Related parts for S3006

S3006 Summary of contents

Page 1

... The very low jitter ECL interface guarantees compli- ance with the bit-error rate requirements of the Bellcore, ANSI, and ITU-T standards. The S3005/ S3006 SETI and SERI chipset is packaged mil pitch, 68-pin LDCC or 25 mil pitch, 80 PQFP package, offering designers a small package outline. ...

Page 2

... An STS- N signal is made byte-interleaved STS-1 signals. The optical counter- part of each STS- N signal is an optical carrier level- N signal (OC The S3005/S3006 chipset supports OC-3 rates (155.52 Mbit/s) and OC-12 (622.08 Mbit/s) rates. Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for STS-3 consists of nine transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes ...

Page 3

... Operation of the S3005/S3006 chips is straightfor- ward. The sequence of operations is as follows: Transmitter 1. 8-bit parallel input 2. Parallel-to-serial conversion 3 ...

Page 4

... Loopback modes are provided for diagnostic loopback (transmitter to receiver), or line loopback (receiver to transmitter) when used with the compat- ible S3006. (See Other Operating Modes.) The operating mode is selected by three mode pro- gramming inputs to be 622.08 Mbit/s, 155.52 Mbit/s, 155.52 Mbit/s with Coded-Mark-Inversion (CMI) en- coding, or 139 ...

Page 5

... S3005 device. Table 3. Reference Frequency Options Table 4. E4CMI Reference Frequency Options Table 5. Reference Jitter Limits Maximum Reference Clock Jitter in 12 KHz to 1 MHz Band OPERATING MODE STS–12 STS–3 CMI STS–3 E4 CMI S3005/S3006 ...

Page 6

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER S3006 RECEIVER FUNCTIONAL DESCRIPTION The S3006 SERI receiver chip provides the first stage of digital processing of a receive SONET STS- 12, STS-3, or ITU-T E4 bit serial stream. It converts the bit-serial 622.08, 155.52, or 139.264 Mbit/s data stream into 78 Mbyte/s, 19 Mbyte/ Mbyte/s byte-serial data format depending on the control set- tings and reference frequency provided by the user ...

Page 7

... Once down-stream overhead circuitry has verified that f3 ft frame and byte synchronization are correct, the OOF input can be set low to disable the frame search process f3 ft from trying to synchronize to a mimic frame pattern. (kHz) (kHz) 6 250 S3005/S3006 7 ...

Page 8

... Figure 8. Loopback Diagram Data Control S3005 S3006 Data Out CLK 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 Data Out S3006 CLK S3005 Data In Control Applied Micro Circuits Corporation ...

Page 9

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER The CMI decoder block on the S3006 SERI accepts serial data from the RSDP/N input at the TSCLK rate (311.04 MHz or 278.528 MHz). The data is then de- coded from CMI to NRZ format and converted from serial to parallel at one half the TSCLK rate. ...

Page 10

... S3005/S3006 S3005 Pin Assignment and Descriptions SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 Applied Micro Circuits Corporation ...

Page 11

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER S3005 Pin Assignment and Descriptions (Continued Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 S3005/S3006 ...

Page 12

... S3005/S3006 S3005 Pin Assignment and Descriptions (Continued – – – – – – – – – – – 12 SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER – – 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 µ ± – – Applied Micro Circuits Corporation ...

Page 13

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER S3006 Pin Assignment and Descriptions Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 S3005/S3006 " " " " ...

Page 14

... S3005/S3006 S3006 Pin Assignment and Descriptions (Continued SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 – Applied Micro Circuits Corporation ...

Page 15

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER S3006 Pin Assignment and Descriptions (Continued – – – – – – – Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 – – S3005/S3006 µ ± – – ...

Page 16

... S3005/S3006 S3006 Pin Assignment and Descriptions (Continued – – – – 16 SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 Applied Micro Circuits Corporation ...

Page 17

... Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 35 51 .300 – 400 min ceramic side 17 1 0.050 ± .005 Capacitor . +.015 .950 –.010 .300 – 400 min Capacitor .055 ± .010 .055 ± .005 COPLANAR TO .004 1.180 ± .020 S3005/S3006 . ...

Page 18

... S3005/S3006 80 PQFP Package Embedded 10 Heatsink Top View 20 All dimensions nominal in mm. S3005 and S3006 80 PQFP Pinouts CAP1 1 CAP1 2 NC AVEE3 4 AGND3 TESTEN 6 ECLGND VEE 8 S3005 RSTB REFSEL1 10 Embedded REFSEL0 DLEB 12 Heatsink NC VEE 14 ECLGND PCLK 16 BYTCLKIP PAE 18 ECLGND TTLGND 20 18 SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER ...

Page 19

... ECL Data Output Jitter (S3005 TSDP/N, DLDP/N) OC–3/STS–3 OC–STS–3 CMI 1 OC–12/STS-12 Reference Clock Frequency Tolerance Clock Synthesis S3005 REFCKINP/N -20 S3006 REFCKINP/N -100 OC–3/STS–3 & OC–12/STS–12 Capture Range Lock Range 2 Acquisition Lock Time OC-3/STS-3 OC-STS-3 CMI OC-12/STS-12 ...

Page 20

... Ambient Temperature <0˚C. Thermal Management Device Package jc S3005 68 LDCC 2.5˚C/W w/45-20 HS S3005 80 TEP 2.0˚C/W w/45-28 HS S3006 68 LDCC 2.5˚C/W w/45-20 HS S3006 80 TEP 2.0˚C/W w/45- SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER PARAMETER Min -55 -55 -65 -0.5 +0.5 -0.5 -3 Min PARAMETER ...

Page 21

... Single Ended ECL Inputs 2. Differential ECL Inputs 3. Standard ECL Outputs 4. Source Terminated Differential ECL Compatible Outputs 5. S3005 Signals 6. S3006 Signals 7. These conditions will be met with an airflow of 400 LFPM. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 1 ...

Page 22

... S3005/S3006 Table 8. S3005 AC Timing Characteristics ( -5. Symbol Description TSCLK Frequency (nom. 155, 311, or 622 MHz) TSCLK Duty Cycle PICLK Duty Cycle tS PIN [7.0] Set-up Time w.r.t. PICLK PIN tH PIN [7.0] Hold Time w.r.t. PICLK PIN tS LLD Set-Up Time w.r.t. LLCLK ...

Page 23

... When a hold time is specified between a data input and a clock input, the hold time is the time in picoseconds from the crossover point of the differential clock input to the crossover point of the differential data input. Table 11. S3006 External Clock Mode Timing Symbol Description REFCLK Freq. (Nominally 622/311//155 MHz) ...

Page 24

... FP pulse or until OOF goes low, which- ever occurs last. Figure 17 shows a typical OOF timing pattern which occurs when the S3006 is con- nected to a down stream section terminating device. OOF remains high for one full frame after the first FP pulse ...

Page 25

... Driver) to REFCLK Input 330 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 50 100 100 330 VEE 330 VEE S3005 DLDP/N to S3006 DLDP/N Fiber Optic Receiver to S3006 RSDP/N S3005/S3006 Internal 100 termination Electrical to optical Internal 100 termination 25 ...

Page 26

... S3005/S3006 STS-12/STS-3 OPTICAL INTERFACE The S3005 and S3006 devices are designed to in- terface seamlessly to make a SONET transceiver for STS-12, CMI-encoded STS-3, and STS-3. Figure 20 shows these two devices connected together with Figure 20. OC-12 Application STS-3 TX STS-3 RX STS-3 CMI ELECTRICAL INTERFACE With the S3006 devices optioned for CMI-coded ...

Page 27

... SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER EXTERNAL CLOCK APPLICATION The S3006 can receive data at SONET or other standard data rates by bypassing the internal clock recovery PLL and supplying the appropriate clock to the REFCLK input. Figure 22 shows an application Figure 22. OC-12 External Clock Application TX Overhead ...

Page 28

... S3005/S3006 Ordering Information GRADE TRANSMITTER S – commercial GRADE TRANSMITTER S – commercial Grade Part number Applied Micro Circuits Corporation • 6195 Lusk Blvd., San Diego, CA 92121 Phone: (619) 450-9333 Fax: (619) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...

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