S2042B-10 AMCC (Applied Micro Circuits Corp), S2042B-10 Datasheet

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S2042B-10

Manufacturer Part Number
S2042B-10
Description
HIGH PERFORMANCE SERIAL INTERFACE CIRCUIT
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
FEATURES
APPLICATIONS
High-speed data communications
Figure 1. System Block Diagram
PRELIMINARY
DEVICE SPECIFICATION
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
BiCMOS PECL CLOCK GENERATOR
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
• Functionally compliant with ANSI X3T11 Fibre
• S2042 transmitter incorporates phase-locked loop
• S2043 receiver PLL configured for clock and
• 1062, 531 and 266 Mb/s operation
• 10- or 20-bit parallel TTL compatible interface
• 1 watt typical power dissipation for chipset
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
• Supercomputer/Mainframe
• Workstation
• Switched networks
• Proprietary extended backplanes
• Mass storage devices/RAID drives
Channel physical and transmission protocol
standards
(PLL) providing clock synthesis from low-speed
reference
data recovery
power supply
Controller
Channel
Fibre
Control
S2043
S2036
S2042
(OFC)
Open
Fiber
RX
TX
Optical
TX
Optical
RX
GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062, 531 or 266 Mbit/s data rates with
associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2043
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics. The TTL
I/O section can operate from either a +3.3V or a +5V
power supply. With a 3.3V power supply the chipset
dissipates only 1W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset. The chipset is compatible with
AMCC’s S2036 Open Fiber Control (OFC) device.
Optical
RX
Optical
TX
S2042
Control
S2036
S2043
(OFC)
Open
Fiber
TX
RX
Controller
Channel
S2042/S2043
Fibre
S2042/S2043
®
1

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S2042B-10 Summary of contents

Page 1

PRELIMINARY DEVICE SPECIFICATION HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK GENERATOR HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards • S2042 transmitter incorporates phase-locked loop (PLL) providing clock ...

Page 2

S2042/S2043 OVERVIEW The S2042 transmitter and S2043 receiver provide serialization and deserialization functions for block- encoded data to implement a Fibre Channel interface. Operation of the S2042/S2043 chips is straightfor- ward, as depicted in Figure 2. The sequence of operations ...

Page 3

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Parallel/Serial Conversion The parallel-to-serial converter takes in 10-bit or 20- bit wide data from the input latch and converts serial data stream. Parallel data is latched into the transmitter on the positive ...

Page 4

S2042/S2043 Figure 5. Functional Waveform S REFCLK (Input PARALLEL 4 DATA BUS K28.5, (Input) Byte Data SERIAL DATA S RCLK (Output) 2 SYNC 0 (Output) 4 PARALLEL 3 DATA BUS (Output) Table 3. Data Mapping ...

Page 5

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Figure 6. Loopback Interface Diagram Data In S2042 OE0, OE1 Fibre Channel Channel Receiver Transmitter S2043 Fibre Channel Data Out Transmitter Receiver CLK When framing is disabled by low SYNCEN, the S2043 simply achieves bit ...

Page 6

S2042/S2043 S2042 Pin Assignment and Descriptions ...

Page 7

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042 Pin Assignment and Descriptions (Continued ...

Page 8

S2042/S2043 S2043 Pin Assignment and Descriptions ...

Page 9

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2043 Pin Assignment and Descriptions (Continued ...

Page 10

S2042/S2043 Figure 7. 52 PQFP Pinouts OE1 1 OE0 2 ECLIOVCC 3 TLY 4 TLX 5 ECLIOVEE 6 S2042 ECLIOVEE ECLIOVCC 10 TOP VIEW TCLKN 11 TCLK 12 ECLVEE 13 TTLVCC= +5V or +3.3V AVCC= ...

Page 11

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Figure 8. 52 PQFP Package Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 S2042/S2043 11 ...

Page 12

S2042/S2043 Absolute Maximum Ratings Case Temperature under Bias Junction Temperature under Bias Storage Temperature Voltage on VCC with Repect to GND Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source ...

Page 13

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042 DC Characteristics Parameters Description Output HIGH Voltage (TTL – 3.3V Power Supply – 3.3V Power Supply – 5V Power Supply Output LOW Voltage (TTL – 3.3V Power Supply – 5V ...

Page 14

S2042/S2043 Table 5. AC Characteristics Parameters Description T REFCLK to TCLK 1 T Data setup w.r.t. REFCLK 2 T Data hold w.r.t. REFCLK 3 T Data setup w.r.t. TCLK 4 T Data hold w.r.t. TCLK TCLK rise ...

Page 15

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Figure 9. Transmitter Timing Diagram (531, 266 Mbits/sec, 10-bit mode) REFCLK 10 BIT DATA (D10-D19) TCLKN TCLK SERIAL DATA OUT Figure 10. Transmitter Timing Diagram (531, 266 Mbits/sec, 20-bit mode) REFCLK 20 BIT DATA TCLKN ...

Page 16

S2042/S2043 Figure 11. Transmitter Timing Diagram (1062 Mbits/sec, 10-bit mode) REFCLK (106.25 MHz) 10 BIT DATA TCLKN (53.125 MHz) TCLK (53.125 MHz) SERIAL DATA OUT Figure 12. Transmitter Timing Diagram (1062 Mbits/sec, 20-bit mode) REFCLK (53.125 MHz) 20 BIT DATA ...

Page 17

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Figure 13. Receiver Timing Diagram (531, 266 Mbits/sec, 10-bit mode) SERIAL DATA IN D10 REFCLK RCLKN RCLK 10 BIT DATA SYNC Figure 14. Receiver Timing Diagram (531 Mbits/sec, 20-bit mode) SERIAL DATA IN D0 REFCLK ...

Page 18

S2042/S2043 Figure 15. Receiver Timing Diagram (1062 Mbits/sec, 10-bit mode) SERIAL DATA IN REFCLK (106.25 MHz) RCLKN (53.125 MHz) RCLK (53.125 MHz) 10 BIT DATA SYNC Figure 16. Receiver Timing Diagram (1062 Mbits/sec, 20-bit mode) SERIAL DATA IN REFCLK (53.125 ...

Page 19

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS Figure 17. Serial Input Rise and Fall Time 80% 50% 20 Figure 18. Serial Output Load 2.0V DD Figure 19.TTL Input and Output Rise and Fall Time 90% ...

Page 20

... S – commercial GRADE S – commercial Example: S2042B-05 — S2042 PQFP package operating at 531 or 266 Mbit/sec rates. Applied Micro Circuits Corporation • 6195 Lusk Blvd., San Diego, CA 92121 Phone: (619) 450-9333 Fax: (619) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...

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