S3038TB AMCC (Applied Micro Circuits Corp), S3038TB Datasheet

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S3038TB

Manufacturer Part Number
S3038TB
Description
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

Specifications of S3038TB

Case
BGA

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Part Number:
S3038TB
Manufacturer:
AMCC
Quantity:
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FEATURES
APPLICATIONS
September 16, 1999 / Revision B
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
BiCMOS LVPECL CLOCK GENERATOR
• Complies with Bellcore and ITU-T
• Supports 622.08 Mbps (OC-12)
• Quad transmitter incorporating phase-locked
• Quad receiver PLL provides clock and
• Selectable reference frequencies of 38.88
• Interface to both LVPECL and TTL logic
• 8-bit TTL datapath
• Compact 23mm x 23mm 208 TBGA package
• Diagnostic loopback mode
• Low jitter LVPECL interface
• Single 3.3V supply
• Local Loopback
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
specifications
loop (PLL) clock synthesis from a low speed
reference clock
data recovery
MHz, or 77.76 MHz
GENERAL DESCRIPTION
The S3038 SONET/SDH Quad transceiver chip is a
fully integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) interface device. The chip per-
forms
parallel-to-serial functions in conformance with SO-
NET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3038 Quad
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3038 also per-
forms SONET/SDH frame detection. The chip can be
used with a 38.88 MHz, or 77.76 MHz reference
clock, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3038 is packaged in a
23mm x 23mm 208 TBGA.
all
necessary
serial-to-parallel
S3038
S3038
S3038
and
®
1

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S3038TB Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-12 QUAD TRANSCEIVER BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-12 QUAD TRANSCEIVER SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Complies with Bellcore and ITU-T specifications • Supports 622.08 Mbps (OC-12) • Quad transmitter incorporating phase-locked loop (PLL) clock ...

Page 2

S3038 Figure 1. System Block Diagram S3038 8 SONET/SDH Transceiver SONET/SDH Transceiver 8 B Network Interface Processor 8 SONET/SDH Transceiver SONET/SDH Transceiver SONET/SDH/ATM OC-12 QUAD TRANSCEIVER 2 2 OTX ORX 2 ...

Page 3

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Figure 2. S3038 Input/Output Diagram RESET REFCLK CLKSEL TMODE PCLK PINA[7:0] 8 PICLKA PINB[7:0] 8 PICLKB PINC[7:0] 8 PICLKC PIND[7:0] 8 PICLKD POUTA[7:0] 8 POCLKAP/N FPA POUTB[7:0] 8 POCLKBP/N FPB POUTC[7:0] 8 POCLKCP/N FPC POUTD[7:0] 8 ...

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S3038 Figure 3. Transmitter Block Diagram CH_LOCK REFCLK CLKSEL CH_LOCK TMODE 8 PINA[7:0] FIFO (input PICLKA 8 PINB[7:0] FIFO (input PICLKB 8 PINC[7:0] FIFO (input PICLKC 8 PIND[7:0] ...

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SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Figure 4. Receiver Block Diagram REFCLK FPA FIFO (output POUTA[7:0] POCLKAP/N FPB FIFO (output) 8 POUTB[7:0] POCLKBP/N FPC FIFO (output) 8 POUTC[7:0] POCLKCP/N FPD FIFO (output) 8 POUTD[7:0] POCLKDP/N CH_LOCK September 16, 1999 / ...

Page 6

S3038 SONET OVERVIEW Synchronous Optical Network (SONET stan- dard for connecting one fiber system to another at the optical level. SONET, together with the Synchro- nous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard ...

Page 7

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER S3038 OVERVIEW The S3038 quad transceiver implements SONET/ SDH serialization/deserialization, transmission, and frame detection/recovery functions. This chip can be used to implement the front end of SONET equip- ment, which consists primarily of the serial transmit ...

Page 8

S3038 FUNCTIONAL DESCRIPTION QUAD TRANSMITTER OPERATION The S3038 quad transceiver chip performs the seri- alizing stage in the processing of a transmit SONET STS-12 bit serial data stream. It converts the 8-bit parallel 77.76 Mbyte/sec data stream into a bit ...

Page 9

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER The following figures illustrate the broad range of transmit data clocking options supported by the S3038. Figure 7 demonstrates the flexibility afforded by the S3038. A low jitter reference is provided directly to the S3038 at ...

Page 10

S3038 RECEIVER OPERATION The S3038 quad transceiver chip provides the first stage of digital processing of a receive SONET STS- 12 bit-serial stream. It converts the bit-serial 622.08 Mbps data stream into a 77.76 Mbyte/sec 8-bit paral- lel data format. ...

Page 11

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Frame and Byte Boundary Detection The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by three consecutive A2 bytes. Framing pattern detection is enabled and dis- abled ...

Page 12

S3038 Table 4. Transmitter Input Signals Pin Assignment and Descriptions ...

Page 13

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Table 5. Transmitter Output Signals Pin Assignment and Descriptions ...

Page 14

S3038 Table 7. Receiver Output Signals Pin Assignment and Descriptions ...

Page 15

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Table 7. Receiver Output Signals Pin Assignment and Descriptions (Continued ...

Page 16

S3038 Table 8. Receiver Input Signals Pin Assignment and Description ...

Page 17

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Table 9. Receiver Control Signals Pin Assignment and Descriptions Table 10. Power and ...

Page 18

S3038 Figure 10. Quad Transceiver Pinout-Bottom View ...

Page 19

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Figure 11. 208 TBGA Package Thermal Management September 16, 1999 / Revision ...

Page 20

S3038 Table 11. Performance Specifications ...

Page 21

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Table 12. Absolute Maximum Ratings ...

Page 22

S3038 Table 15. TTL Input/Output DC Characteristics ...

Page 23

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Figure 12. Differential Voltage V(+) V(–) V(+) – V(–) Note: V(+) – V(-) is the algebraic difference of the input signals. September 16, 1999 / Revision B V SWING SWING ...

Page 24

S3038 Table 18. Receiver Timing (See Figure 13 ...

Page 25

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Figure 15. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 0) REFCLK PINx[7:0] SERIAL DATA OUT Table 20. S3038 Transmitter Timing (Normal or Channel Lock Mode, TMODE = ...

Page 26

S3038 Table 22. Power and Ground Application Information ...

Page 27

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER RECEIVER FRAMING Figure 17 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF and remains enabled while OOF is ...

Page 28

S3038 Figure 20. External Loop FIlter Figure 21. Serial Output Load Figure 22. High Speed Differential Inputs 28 SONET/SDH/ATM OC-12 QUAD TRANSCEIVER 22 nF 270 270 CAP1 CAP2 1.5k 1.5k Vcc - 1.3 V 0.01 F 100 0.01 F 0.01 ...

Page 29

SONET/SDH/ATM OC-12 QUAD TRANSCEIVER Ordering Information – 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) ...

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