AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 226
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AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
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Figure 19-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
19.10.7.2
Figure 19-13. Internal Address Usage
19.11 Using the Peripheral DMA Controller
32059L–AVR32–01/2012
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
10-bit Slave Addressing
DADR
DADR
DADR
W
W
W
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (IADR). The two remaining Inter-
nal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave
Addressing.
Example: Address a 10-bit device:
(10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
Figure 19-13
the use of internal addresses to access the device.
The use of the Peripheral DMA Controller significantly reduces the CPU load.
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
S
T
A
R
T
A
A
A
M
S
B
Address
Device
IADR(23:16)
IADR(15:8)
IADR(7:0)
0
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
S
B
L
W
W
R
E
T
R
I
/
A
C
K
WORD ADDRESS
A
A
A
M
S
B
FIRST
IADR(15:8)
Sr
IADR(7:0)
DADR
A
C
K
WORD ADDRESS
SECOND
A
A
R
Sr
IADR(7:0)
A
L
S
B
A
C
K
DADR
DATA
DATA
A
Sr
R
A
C
K
S
O
P
T
N
A
DADR
DATA
P
DATA
R
N
P
N
A
P
226
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