AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 377
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AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 377 of 684
- Download datasheet (11Mb)
32059L–AVR32–01/2012
RXOUTI
FIFOCON
RXOUTI
FIFOCON
OUT
OUT
•Detailed description
(bank 0)
(bank 0)
DATA
DATA
Figure 22-20. Example of an OUT Endpoint with one Data Bank
Figure 22-21. Example of an OUT Endpoint with two Data Banks
The data is read, following the next flow:
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set immediately.
• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user can read the byte count of the current bank from BYCT to know how many bytes to
• The user reads the data from the current bank by using the USBFIFOnDATA register (see
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
RXOUTE is one.
read, rather than polling RWALL.
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
expected data frame is read or the bank is empty (in which case RWALL is cleared and
BYCT reaches zero).
HW
ACK
ACK
HW
SW
read data from CPU
SW
BANK 0
OUT
NAK
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
471), until all the
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
377
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