AT32UC3B1256 Atmel Corporation, AT32UC3B1256 Datasheet - Page 325

• Manufacturer Part Number: AT32UC3B1256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.6.9.4
21.6.9.5
21.6.9.6
21.6.10
21.6.11
21.6.11.1
21.6.11.2
32059L–AVR32–01/2012
Test Modes
Receiver and Transmitter Control
Receiver Time-out
Character Transmission and Reception
Normal Mode
Automatic Echo Mode
See
In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one, is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a
transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent
while THR is empty, and TXD will be high during character transmission, as if 0xFF was being
sent. If a new character is written to THR it will be sent correctly during the next transmission
slot. Writing a one to CR.RSTSTA will clear CSR.UNRE. To ensure correct behavior of the
receiver in SPI slave mode, the master device sending the frame must ensure a minimum delay
of one bit period in between each character transmission.
Receiver Time-out’s are not possible in SPI mode as the baud rate clock is only active during
data transfers.
The internal loopback feature enables on-board diagnostics, and allows the USART to operate
in three different test modes, with reconfigured pin functionality, as shown below.
During normal operation, a receivers RXD pin is connected to a transmitters TXD pin.
Figure 21-39. Normal Mode Configuration
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it
is also sent to the TXD pin, as shown in
”Transmitter Operations” on page
Transmitter
Receiver
304, and
Figure
21-40. Transmitter configuration has no effect.
”Receiver Operations” on page
RXD
TXD
311.
325