AT32UC3B1256 Atmel Corporation, AT32UC3B1256 Datasheet - Page 363
AT32UC3B1256
Manufacturer Part Number
AT32UC3B1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUR
Manufacturer:
OMRON
Quantity:
12 000
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 363 of 684
- Download datasheet (11Mb)
22.7.1.5
22.7.1.6
32059L–AVR32–01/2012
Speed control
DPRAM management
•USB Suspend mode
•Device mode
•Host mode
Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger
the USB interrupt:
In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register
(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the USB Data
UTMI transceiver is automatically set in suspend mode to reduce the consumption.
When the USBB interface is in device mode, the speed selection (full-/low-speed) depends on
which of D+ and D- is pulled up. The LS bit allows to connect an internal pull-up resistor either
on D+ (full-speed mode) or on D- (low-speed mode). The LS bit shall be written before attaching
the device, what can be done by clearing the DETACH bit in UDCON.
Figure 22-7. Speed Selection in Device Mode
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the connected device, which is reflected by the
Speed Status (SPEED) field in USBSTA.
Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The user shall therefore configure them in the same order.
The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint
n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a
• The ID Transition Interrupt (IDTI)
• The VBus Transition Interrupt (VBUSTI)
• The Wake-up Interrupt (WAKEUP)
• The Host Wake-up Interrupt (HWUPI)
VBUS
D+
D-
UDCON.DETACH
UDCON.LS
363
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