AT32UC3B1256 Atmel Corporation, AT32UC3B1256 Datasheet - Page 536

• Manufacturer Part Number: AT32UC3B1256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.11
Name:
Access Type:
Offset:
Reset Value:
• CPRD: Channel Period
32059L–AVR32–01/2012
31
23
15
7
Only the first
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated:
Channel Period Register
20
30
22
14
6
bits (internal channel counter size) are significant.
CPRDx
Read/Write
0x208
0x00000000
– By using the Master Clock (CLK_PWM) divided by an X given prescaler value (with
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
– By using the Master Clock (CLK_PWM) divided by an X given prescaler value (with
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula
will be:
becomes, respectively:
X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula
will be:
becomes, respectively:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
CLK_PWM
X CPRD
CRPD
2 X CPRD
2 CPRD DIVA
CLK_PWM
CLK_PWM
×
×
29
21
13
×
5
CLK_PWM
×
×
DIVA
)
×
)
)
or
)
28
20
12
4
(
--------------------------------------------- -
or
CRPD
CLK_PWM
(
--------------------------------------------------- -
2 CPRD
CPRD
CPRD
CPRD
CPRD
×
×
CLK_PWM
DIVAB
×
27
19
11
)
DIVB
3
)
26
18
10
2
25
17
9
1
24
16
8
0
536