AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 139

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.5
9.5.6
32117C–AVR-08/11
AST wakeup
Digital tuner
The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register
is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable
(EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD)
register.
The AST can wake up the CPU directly, without the need to trigger an interrupt. A wakeup can
be generated when the counter overflows, when the counter reaches the selected alarm value,
or when the selected prescaler bit has a 0-to-1 transition. In this case, the CPU will continue
executing from the instruction following the sleep instruction.
The AST wakeup is enabled by writing a one to the corresponding bit in the Wake Enable Regis-
ter (WER). When the CPU wakes from sleep, the wake signal must be cleared by writing a one
to the corresponding bit in SCR to clear the internal wake signal to the sleep controller. If the
wake signal is not cleared after waking from sleep, the next sleep instruction will have not effect
because the CPU will wake immediately after this sleep instruction.
The AST wakeup can wake the CPU from any sleep mode where the source clock is active. The
AST wakeup can be configured independently of the interrupt masking.
The digital tuner adds the possibility to compensate for a too slow or a too fast input clock. The
ADD bit in the Digital Tuner Register (DTR.ADD) selects if the tuned frequency should be
reduced or increased. If ADD is ‘0’, the prescaler frequency is reduced:
Where f
EXP are the corresponding fields to be programmed in DTR. Note that DTR.EXP must be
greater than zero. Frequency tuning is disabled by programming DTR.VALUE as zero.
If ADD is ‘1’, the prescaler frequency is increased:
Note that these formulas to be within an error of 0.01%, it is recommended that the prescaler bit
that is used as the clock for the counter (selected by CR.PSEL) or to trigger the periodic interrupt
(selected by PIRn.INSEL) be bit 6 or higher.
TUNED
is the tuned frequency,
f
f
TUNED
TUNED
f
=
=
0
is the original prescaler frequency, and VALUE and
f
f
0
0
⎛
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎝
1
1
–
+
--------------------------------------------------------------------------------
roundup
------------------------------------------------------------------------------- -
roundup
⎛
⎝
⎛
⎝
------------------- -
VALUE
------------------- -
VALUE
256
256
1
1
⎞
⎠
⎞
⎠
⋅
⋅
(
(
2
2
EXP
EXP
AT32UC3C
)
)
+
–
1
1
⎞
⎟
⎟
⎟
⎠
⎞
⎟
⎟
⎟
⎠
139