AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 157

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
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Secure State ........................................................................................... 59
Memory System ..................................................................................... 61
Memory Protection Unit ........................................................................ 66
Instruction Cycle Summary .................................................................. 71
4.4Detailed instruction description ...............................................................................43
5.1Basic concept ..........................................................................................................59
5.2Typical use scenario ................................................................................................59
5.3Secure state boot sequence ....................................................................................60
5.4Secure state debugging ..........................................................................................60
5.5Events in secure state .............................................................................................60
6.1Memory sections .....................................................................................................61
6.2Memory interfaces ...................................................................................................62
6.3IF stage interface .....................................................................................................62
6.4EX stage interfaces .................................................................................................62
6.5IRAM Write buffer ....................................................................................................64
6.6Memory barriers ......................................................................................................64
7.1Memory map in systems with MPU .........................................................................66
7.2Understanding the MPU ..........................................................................................66
7.3Example of MPU functionality .................................................................................70
8.1Definitions ................................................................................................................71
8.2Special considerations ............................................................................................71
8.3CPU revision ...........................................................................................................72
8.4ALU instructions ......................................................................................................72
8.5Multiply instructions .................................................................................................75
8.6MAC instructions .....................................................................................................76
8.7MulMac64 instructions .............................................................................................76
8.8Divide instructions ...................................................................................................77
8.9Saturate instructions ................................................................................................77
8.10Load and store instructions ...................................................................................77
8.11Multiple data memory access instructions .............................................................81
8.12Branch instructions ................................................................................................82
8.13Call instructions .....................................................................................................82
8.14Return from execution mode instructions ..............................................................82
8.15Swap instructions ..................................................................................................83
8.16System register instructions ..................................................................................83
AVR32
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