AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet
AT32UC3L0128
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AT32UC3L0128 Summary of contents
Page 1
... Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – SPI Slaves can be Addressed ® ® AVR Microcontroller 32-bit Atmel AVR Microcontroller AT32UC3L0256 AT32UC3L0128 Summary 32145AS–12/2011 ...
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... Single-pin Programming Trace and Debug Interface Muxed with Reset Pin – NanoTrace Provides Trace Capabilities through JTAG or aWire Interface • 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) • Five High-drive I/O Pins • Single 1.62-3.6 V Power Supply 32145AS–12/2011 2 C-compatible ® ® ® ® QTouch and Atmel AVR QMatrix Touch Acquisition AT32UC3L0128/256 2 ...
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... The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L0128/256 incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. ...
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... Suppression QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The AT32UC3L0128/256 integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System, with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic run- time control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers ...
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... OSC32K XOUT32 OSC0 DFLL PLL INTERRUPT CONTROLLER EXTERNAL INTERRUPT EXTINT[5..1] CONTROLLER NMI PWM CONTROLLER PWMA[35..0] ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER AT32UC3L0128/256 LOCAL BUS LOCAL BUS INTERFACE AVR32UC CPU 32 KB SRAM DATA INTERFACE M S 128/256 KB FLASH REGISTERS BUS PERIPHERAL DMA ...
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... AT32UC3L0256 256KB Digital Frequency Locked Loop 20-150 MHz (DFLL) Phase Locked Loop 40-240 MHz (PLL) Crystal Oscillator 0.45-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) RC Oscillator 32 kHz (RC32K) TQFP48/QFN48/TLLGA48 AT32UC3L0128/256 AT32UC3L0128 128KB 32KB ...
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... The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32145AS–12/2011 TQFP48/QFN48 Pinout AT32UC3L0128/256 Section 3.2. 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 13 PA02 7 ...
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... USART0 USART1 SPI TXD RTS NPCS[2] USART0 USART1 SPI USART1 RXD CTS NPCS[3] CLK AT32UC3L0128/256 GPIO Function E F PWMA PWMA[0] GCLK[0] PWMA ACIFB TWIMS0 PWMA[1] ACAP[0] TWALM PA21 PB10 RESET_N ...
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... SPI TC0 TXD ADP[0] NPCS[0] A1 USART3 ADCIFB SPI TC0 RXD ADP[1] SCK B1 USART3 USART3 SPI TC0 RTS CLK MISO A2 AT32UC3L0128/256 PWMA ACIFB USART0 PWMA[2] ACBP[0] CLK PWMA ACIFB USART0 PWMA[3] ACBN[3] CLK PWMA ACIFB PWMA[4] ACBP[1] PWMA ACIFB TWIMS0 PWMA[5] ACBN[0] ...
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... USART3 CLK0 TXD CLK TC1 USART1 CLK1 RXD TC1 TWIMS1 CLK2 TWALM for a description of the various peripheral signals. ”Electrical Characteristics” on page 30 ”TWI Pin Characteristics(1)” on page 37 AT32UC3L0128/256 TC0 PWMA ACIFB B2 PWMA[26] ACBP[2] TWIMS0 PWMA PWMA TWALM PWMA[27] PWMAOD[27] TWIMS0 PWMA ...
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... JTAG debug port OSC0, OSC32 JTAG Pinout 48-pin Pin name 11 PA00 14 PA01 13 PA02 4 PA03 Nexus OCD AUX Port Connections AXS=1 AXS=0 PA05 PB08 PA10 PB00 PA18 PB04 PA17 PB05 PA16 PB03 PA15 PB02 PA14 PB09 AT32UC3L0128/256 JTAG pin TCK TMS TDO TDI 11 ...
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... PA20 Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA Section 5.1.4 on page 26 Other Functions 48-pin Pin 27 PA11 22 RESET_N 11 PA00 AT32UC3L0128/256 Oscillator Pin XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 for constraints on the WAKE_N pin. Function WAKE_N aWire DATA aWire DATAOUT ...
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... Analog Analog Analog ADC Interface - ADCIFB Analog Output Output Input aWire - AW I/O I/O Capacitive Touch Module - CAT I/O I/O Analog Output Input Output External Interrupt Controller - EIC Input Input Glue Logic Controller - GLOC Input Output JTAG module - JTAG Input Input Output AT32UC3L0128/256 Active Level Comments 13 ...
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... System Control Interface - SCIF Output Input Output Analog/ Digital Analog/ Digital Analog/ Digital Analog Analog Analog Serial Peripheral Interface - SPI I/O I/O I/O I/O Timer/Counter - TC0, TC1 I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWIMS0, TWIMS1 I/O I/O AT32UC3L0128/256 Low Not all channels support open drain mode Low Low 14 ...
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... Power Input Power Input Power Input Power Input Ground Ground Auxiliary Port - AUX Output Output Output Input Low Output Low General Purpose I/O pin I/O I/O AT32UC3L0128/256 Comments 1.62V to 1.98V 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. 1.62V to 1.98V 1.62V to 1.98V (1) 1.62V to 3.6V 15 ...
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... GPIO pins. Selected pins are also SMBus compliant (refer to Section 3.2 on page path to ground when the AT32UC3L0128/256 is powered down. This allows other devices on the SMBus to continue communicating even though the AT32UC3L0128/256 is not powered. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details ...
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... ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 32145AS–12/2011 AT32UC3L0128/256 17 ...
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... Sector lock capabilities, bootloader protection, security bit • 32 fuses, erased during chip erase • User page for data to be preserved during chip erase AT32UC3L0128/256 Physical Memory Map Start Address 0x00000000 0x80000000 ...
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... General-Purpose Input/Output Controller - GPIO Universal Synchronous Asynchronous Receiver USART0 Transmitter - USART0 Universal Synchronous Asynchronous Receiver USART1 Transmitter - USART1 Universal Synchronous Asynchronous Receiver USART2 Transmitter - USART2 Universal Synchronous Asynchronous Receiver USART3 Transmitter - USART3 SPI Serial Peripheral Interface - SPI TWIM0 Two-wire Master Interface - TWIM0 AT32UC3L0128/256 19 ...
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... Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 PWMA Pulse Width Modulation Controller - PWMA TC0 Timer/Counter - TC0 TC1 Timer/Counter - TC1 ADCIFB ADC Interface - ADCIFB ACIFB Analog Comparator Interface - ACIFB CAT Capacitive Touch Module - CAT GLOC Glue Logic Controller - GLOC AW aWire - AW AT32UC3L0128/256 20 ...
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... Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3L0128/256 Local Bus Mode Address Access WRITE 0x40000040 Write-only ...
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... Voltage Regulator The AT32UC3L0128/256 embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load 60mA. The regulator supplies the output voltage on VDDCORE. The regula- tor may only be used to drive internal circuitry in the device. VDDCORE should be externally connected to the 1.8V domains. See Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations ...
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... All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 5-2. 1.98-3.6V VDDCORE 32145AS–12/2011 Figure 5-2 3.3V Single Supply Mode + - VDDIN I/O Pins OSC32K_2, AST, Wake, Regulator regulator VDDANA AT32UC3L0128/256 shows the power schematics to be used for 3.3V VDDIO I/O Pins OSC32K, RC32K, POR33, control SM33 Linear CPU, Peripherals, Memories, SCIF, BOD, RCSYS, ADC ...
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... V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 5-3. 1.98-3.6V 32145AS–12/2011 1.8V Single Supply Mode VDDIN OSC32K_2, AST, Wake, Regulator VDDCORE VDDANA AT32UC3L0128/256 Figure 5-3. All I/O lines will be powered by the VDDIO I/O Pins I/O Pins OSC32K, RC32K, POR33, control SM33 CPU, Peripherals, Memories, ...
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... Supply Mode with 1.8V Regulated I/O Lines + - VDDIN OSC32K_2, AST, Wake, Regulator VDDCORE regulator VDDANA Section 3.2 on page 8 for description of power supply for each I/O line. AT32UC3L0128/256 Figure 5-4. This configuration is required in order to VDDIO I/O Pins I/O Pins OSC32K, RC32K, POR33, control SM33 Linear CPU, ...
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... A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V. • A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V. 5.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3L0128/256. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 5.2.1 ...
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... Programming and Debugging 6.1 Overview The AT32UC3L0128/256 supports programming and debugging through two interfaces, JTAG or aWire. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved ...
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... OS running from the secure part of the bit set flash supports it. Secure Mode SAB Restrictions Name Address Start 0x580000000 0x500000000 0x580800000 - 1. Second Word of the User Page, refer to the Fuses Settings section for details. AT32UC3L0128/256 Address End Access 0x580000000 + Blocked (USERPAGE[15:0] << 10) 0x500000000 + Blocked (USERPAGE[31:16] << 10) 0x581000000 Read ...
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... Security Bit SAB Restrictions Name Address start 0x100000110 0x580800000 - User Code Programming SAB Restrictions Name Address start 0x100000110 0x580800000 0x5FFFE0000 0x580000000 + BOOTPROT size - AT32UC3L0128/256 Address end Access 0x100000118 Read/Write 0x581000000 Read - Blocked Address end Access 0x100000118 Read/Write 0x581000000 Read 0x5FFFE0400 ...
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... DC supply peripheral I/Os and internal regulator, 3.3V supply mode DC supply core Analog supply voltage AT32UC3L0128/256 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or other condi- ...
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... CAT, ACIFB, GCLK4 pin GCLK5 clock frequency GLOC GCLK6 clock frequency GCLK7 clock frequency GCLK8 clock frequency GCLK9 clock frequency FREQM, GCLK0-8 Table 7-5 are measured values of power consumption under the following condi- AT32UC3L0128/256 (1) Rise Rate Min Max Unit 0 2.5 V/µs Slower rise time requires 2.5 V/µ ...
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... VDDCORE • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regula- tor static current = V = 1.8V VDDIN VDDCORE Considerations section for more details • PM, SCIF, AST, FLASHCDW, PBA bridge AT32UC3L0128/256 (Figure 7-2) - used only when noted 32 ...
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... These numbers are valid for the measured condition only and must not be extrapolated to other frequencies. Figure 7-1. 32145AS–12/2011 Measured on (Figure 7-2) (Figure 7-2) Measurement Schematic, Internal Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA AT32UC3L0128/256 Consumption Typ 300 174 Amp0 7.3 6.7 800 ...
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... Figure 7-2. 32145AS–12/2011 Measurement Schematic, External Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA AT32UC3L0128/256 34 ...
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... QFN64 package TQFP48 package QFN48 package TLLGA48 package TQFP64 package QFN64 package TQFP48 package QFN48 package TLLGA48 package TQFP64 package QFN64 package depending on the supply for the pin. Refer to VDDIN VDDIO AT32UC3L0128/256 Min Typ Max 75 100 145 -0.3 0.3*V VDD -0.3 0.3*V VDD V + 0.3 VDD ...
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... Pull-up resistors disabled TQFP48 package QFN48 package TLLGA48 package TQFP64 package QFN64 package TQFP48 package QFN48 package TLLGA48 package TQFP64 package QFN64 package depending on the supply for the pin. Refer to VDDIN VDDIO AT32UC3L0128/256 Min Typ Max 30 50 110 75 100 145 -0.3 0.3*V VDD -0 ...
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... QFN48 package TLLGA48 package TQFP64 package QFN64 package depending on the supply for the pin. Refer to VDDIN VDDIO (1) Condition V = 3.0V VDD V = 1.62V VDD V = 3.6V VDD V = 1.98V VDD V = 3.6V VDD V = 1.98V VDD AT32UC3L0128/256 Min Typ Max 30 50 110 -0.3 0.3*V VDD -0.3 0.3*V VDD 0.7*V 5.5 VDD 0.7*V 5.5 VDD 0.4 0.4 V -0.4 VDD V -0.4 VDD ...
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... Cbus = 400pF, V > 1.62V VDD Cbus = 400pF, V > 2.0V VDD depending on the supply for the pin. Refer to VDDIN VDDIO Conditions (1) TQFP48 package QFN48 package TLLGA48 package TQFP64 package QFN64 package Figure AT32UC3L0128/256 Min Typ Max 0 3.8 3.5 3.5 3.9 3.5 250 470 400 Section 3.2 on page 12 Min ...
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... Active mode 0.45MHz, SCIF.OSCCTRL.GAIN = 0 Active mode 10MHz, SCIF.OSCCTRL.GAIN = 2 Oscillator Connection XOUT C i XIN and the equation above also applies to the 32 KHz oscillator connection. The user can then be found in the crystal datasheet. L AT32UC3L0128/256 ( ) – – PCB is the internal equivalent load capacitance. ...
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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32145AS–12/2011 Conditions R = 60kOhm 9pF S L (2) (2) 32 768Hz Conditions f = 4MHz 16MHz IN AT32UC3L0128/256 Min Typ Max Unit 32 768 Hz (1) 30 000 cycles 6 12 0.6 µ kOhm ...
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... FINE lock 8-150kHz, SSG REF disabled ACCURATE lock 8-150kHz, REF dither clk RCSYS/2, SSG disabled Within 90% of final values f = 32kHz, FINE lock, SSG disabled REF f = 32kHz, ACCURATE lock, dithering REF clock = RCSYS/2, SSG disabled AT32UC3L0128/256 Min Typ Max 20 150 8 150 (3) 0.38 See Figure 7-4 0.1 0.5 0.06 0.5 ...
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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32145AS–12/2011 (1)(2) DFLL Open Loop Frequency variation Tem pera ture Conditions V = 1.8V VDDCORE AT32UC3L0128/256 1,98V 1,8V 1.62V 60 80 Min Typ Max 88 120 152 1.2 ...
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... Conditions Conditions Calibrated at 85°°C gives the device maximum operating frequency depending on the number of flash Read Mode High speed read mode Normal read mode Conditions f = 50MHz CLK_HSB f = 115kHz CLK_HSB AT32UC3L0128/256 Min Typ Max 0.7 100 Min Typ Max 111.6 115 118 ...
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... VDDIN I = 0.1mA to 60mA, OUT V > 1.98V VDDIN ( 0.1mA to 60mA, OUT V < 1.98V VDDIN Normal mode Low power mode Normal mode Low power mode Condition 33. AT32UC3L0128/256 Min Typ Max 100k 10k 15 Min Typ Max 1.98 3.3 3.6 1 Typ Techno. ...
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... These values are not covered by test limits in production. Figure 7-5. V POT+ V POT- 32145AS–12/2011 Condition rising VDDCORE falling VDDCORE Time with VDDCORE < V necessary to generate a reset signal POR18 Operating Principle AT32UC3L0128/256 Min Typ Max 1.45 1.58 1.2 1.32 POT- 460 4 6 Time Units V µs µ ...
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... These values are not covered by test limits in production. Figure 7-6. V POT+ V POT- 32145AS–12/2011 Condition rising VDDIN falling VDDIN Time with VDDIN < V necessary to generate a reset signal POR33 Operating Principle AT32UC3L0128/256 Min Typ Max 1.49 1.58 1.3 1.45 POT- 460 20 400 Time Units V µs µ ...
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... Min Typ Condition T = 25°C Time with VDDCORE < BODLEVEL necessary to generate a reset signal Condition (1) Calibrated , T = 25°C (2) Time with VDDIN < V necessary to generate a reset signal Normal mode Normal mode AT32UC3L0128/256 Max Units 1.60 V 1.69 Min Typ Max Min Typ Max 1.675 1 ...
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... VDDCORE 1.62V to 1.98V VDDIO VDDCORE C ) and a capacitor ( ). In addition, the resistance ( ONCHIP ) of the PCB and source must be taken into account when calculating the required Figure 7-7 shows the ADC input channel equivalent circuit. AT32UC3L0128/256 Min Typ Max Units 6 MHz 6 MHz 6 15 µs 11 ...
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... ONCHIP SOURCE ONCHIP (1) Conditions ADC clock frequency = 6MHz, Input Voltage Range = ADVREFP ADC clock frequency = 6MHz, Input Voltage Range = (10% V ADVREFP (90 ADVREFP ADC clock frequency = 6MHz (1) Conditions ADC clock frequency = 6MHz AT32UC3L0128/256 R ONCHIP C ONCHIP ADCVREFP × SOURCE t ...
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... Gradient I Current consumption TS t Startup time STARTUP Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. 32145AS–12/2011 (1) Conditions ADC clock frequency = 6MHz (1) Condition AT32UC3L0128/256 Min Typ Max Units 8 Bit +/-0.5 -0.3 0.3 LSB +/-1 +/-1 Min Typ ...
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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32145AS–12/2011 Min -0.2 -0.2 = 1.0V, ACREFN = 12MHz, (1) = 12MHz ⎛ ⎝ ---------------------------------------- t CLKACIFB = 3MHz Min AT32UC3L0128/256 Typ Max V + 0.3 VDDIO V - 0.6 VDDIO 000 000 ⎞ 1 × ⎠ ...
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... USB 2.0 electrical specifications. 7.8.10.1 Electrical Characteristics Table 7-37. Electrical Parameters Symbol Parameter Recommended external USB R EXT series resistor 32145AS–12/2011 Min Typ Conditions Min In series with each USB pin with ±5% AT32UC3L0128/256 Max Unit 1 kOhm 1 Typ Max Unit 39 Ohm 52 ...
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... From wake-up event to the first instruction of an interrupt routine entering the decode stage of the CPU. From wake-up event to the first instruction entering the decode stage of the CPU. (1) Conditions AT32UC3L0128/256 t 7-38. is the period of the CPU clock CPU ”Oscillator Characteristics” on page t Max (in µ ...
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... USART in SPI Master Mode with (CPOL= 0 and CPHA (CPOL= 1 and CPHA= 0) USPI3 USPI5 (1) Conditions V VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF t ⎛ ⎞ 1 SPCK × t – ⎝ ------------------------------------ ⎠ CLKUSART × CLKUSART AT32UC3L0128/256 USPI1 USPI4 Min Max (2) 28 SAMPLE from 0 16.5 (2) 25 SAMPLE 0 21.19 Units ns 54 ...
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... MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending the SPI slave response time. Please refer to the SPI slave VALID the maximum frequency of the CLK_SPI. Refer to the SPI chap- VALID CLKSPI CPHA= 0) USPI6 USPI7 USPI8 AT32UC3L0128/256 × CLKSPI , ( , ----------- - ---------------------------- - ) PINMAX SPIn 9 is the maximum frequency of the CLK_SPI ...
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... SPCK 32145AS–12/2011 USPI9 USPI10 USPI11 USPI12 USPI14 (1) Conditions V VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF t ⎛ ⎞ 1 SPCK × t – ⎝ ------------------------------------ ⎠ CLKUSART × CLKUSART AT32UC3L0128/256 USPI13 USPI15 Min (2) 2 SAMPLE t CLK_USART 0 from (2) 2 SAMPLE t CLK_USART 0 27.2 0 27.2 0 Max Units 37.3 37 ...
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... CLK_SPI. Refer to the SPI CLKSPI f CLKSPI f MIN ---------------------------- - SPCKMAX SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris- SPI0 SPI2 AT32UC3L0128/256 × CLKSPI MIN ( ---------------------------- - , ----------- - ) SPIn 9 × ...
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... MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. f SPCKMAX SPIn is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending the SPI slave response time. Please refer to the SPI slave VALID t . VALID AT32UC3L0128/256 SPI4 Min 33 )/2 CLK_SPI from 0 )/2 29 CLK_SPI ...
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... SPCK MISO MOSI Figure 7-16. SPI Slave Mode with (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI Figure 7-17. SPCK, CPOL=0 SPCK, CPOL=1 NPCS 32145AS–12/2011 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 SPI Slave Mode, NPCS Timing SPI12 SPI14 AT32UC3L0128/256 SPI13 SPI15 59 ...
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... CLKSPI f MIN f = SPCKMAX SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. shows the TWI-bus timing requirements and the compliance of the device with and and f ) requires user intervention through appropriate programming of the relevant TWCK AT32UC3L0128/256 Min 0 6.0 from 0 5.5 3.4 1.1 3.3 0.7 1 MIN f ...
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... Standard - Fast > 100 kHz f 100 kHz ; fast mode: TWCK = period of TWI internal prescaled clock (see chapters on TWIM and TWIS) has only to be met if the device does not stretch the LOW period (t HD;DAT AT32UC3L0128/256 Maximum Device Requirement 1000 300 b 300 300 ...
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... These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess technology. These values are not covered by test limits in production. 32145AS–12/2011 JTAG2 TCK JTAG0 JTAG3 TDO JTAG5 JTAG6 JTAG7 Conditions V from VDDIO 3.0V to 3.6V, maximum external capacitor = 40pF AT32UC3L0128/256 JTAG1 JTAG4 JTAG8 JTAG9 JTAG10 Min Max 21.8 8.6 30.3 2.0 2.3 9.5 21.8 0.6 6.9 9.3 32.2 Units ...
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... × θ ( θ HEATSINK JC 8-1. = cooling device thermal resistance (°C/W), provided in the device datasheet. AT32UC3L0128/256 Condition Package Still Air TQFP48 TQFP48 Still Air QFN48 QFN48 Still Air TLLGA48 TLLGA48 , in °C can be obtained from the following: J Typ Unit 54.4 °C/W 15.7 26.0 ° ...
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... Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32145AS–12/2011 AT32UC3L0128/256 mg MSL3 MS-026 E3 64 ...
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... Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32145AS–12/2011 AT32UC3L0128/256 mg MSL3 M0-220 E3 65 ...
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... Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32145AS–12/2011 AT32UC3L0128/256 mg MSL3 N ...
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... Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature A maximum of three reflow passes is allowed per component. 32145AS–12/2011 gives the recommended soldering profile from J-STD-20. Soldering Profile AT32UC3L0128/256 Green Package 3°C/s max 150-200°C 60-150 260°C 6°C/s max ...
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... Ordering Code AT32UC3L0256-AUTES AT32UC3L0256-AUT AT32UC3L0256-AUR AT32UC3L0256-ZAUTES AT32UC3L0256 AT32UC3L0256-ZAUT AT32UC3L0256-ZAUR AT32UC3L0256-D3HES AT32UC3L0256-D3HT AT32UC3L0256-D3HR AT32UC3L0128-AUT AT32UC3L0128-AUR AT32UC3L0128-ZAUT AT32UC3L0128 AT32UC3L0128-ZAUR AT32UC3L0128-D3HT AT32UC3L0128-D3HR 32145AS–12/2011 Carrier Type Package Package Type ES Tray TQFP 48 Tape & Reel JESD97 Classification E3 ES Tray QFN 48 Tape & Reel ES Tray ...
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... SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 32145AS–12/2011 AT32UC3L0128/256 69 ...
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... SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 10.1.5 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph- 32145AS–12/2011 AT32UC3L0128/256 70 ...
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... Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature 32145AS–12/2011 AT32UC3L0128/256 ---------------- - ...
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... When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate 32145AS–12/2011 AT32UC3L0128/256 72 ...
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... Busy/Ready bit is started, wait until the ready bit is low in the Sta- tus Register before enabling the interrupt. 10.2 Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround 32145AS–12/2011 AT32UC3L0128/256 73 ...
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... Debug Interface chapter. Fix/Workaround MEMORY_SPEED_REQUEST command and use this formula instead: 32145AS–12/2011 AT32UC3L0128/256 ...
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... Sleepwalking in idle and frozen sleep mode will mask all other PB clocks 32145AS–12/2011 Flash Characteristics Parameter Page programming time Page erase time Fuse programming time Full chip erase time (EA) JTAG chip erase time (CHIP_ERASE) AT32UC3L0128/256 Conditions Min Typ 7.5 7 50MHz CLK_HSB 1 ...
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... RCSYS by writing to the RCCR register in SCIF. 5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca- tion in the SCIF memory range. Fix/Workaround 32145AS–12/2011 AT32UC3L0128/256 76 ...
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... PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 32145AS–12/2011 AT32UC3L0128/256 77 ...
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... Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 4. TWIS stretch on Address match error 32145AS–12/2011 AT32UC3L0128/256 78 ...
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... This results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 32145AS–12/2011 AT32UC3L0128/256 79 ...
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... PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V. Fix/Workaround None pull-up on pins that are not bonded PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current consumption on VDDIO/VDDIN if left undriven. Fix/Workaround 32145AS–12/2011 AT32UC3L0128/256 ---------------- - sab CV 3 – ...
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... Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the GPIO. 3. PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. 32145AS–12/2011 AT32UC3L0128/256 81 ...
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... Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. A – 05/2010 1. 32145AS–12/2011 Initial revision. AT32UC3L0128/256 82 ...
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... Embedded Memories ......................................................................................18 4.2 Physical Memory Map .....................................................................................18 4.3 Peripheral Address Map ..................................................................................19 4.4 .........................................................................................................................20 4.5 CPU Local Bus Mapping .................................................................................20 5.1 Supply Considerations .....................................................................................22 5.2 Startup Considerations ....................................................................................26 6.1 Overview ..........................................................................................................27 6.2 Service Access Bus .........................................................................................27 7.1 Absolute Maximum Ratings* ...........................................................................30 7.2 Supply Characteristics .....................................................................................30 7.3 Maximum Clock Frequencies ..........................................................................31 7.4 Power Consumption ........................................................................................31 7.5 I/O Pin Characteristics .....................................................................................35 7.6 Oscillator Characteristics .................................................................................38 7.7 Flash Characteristics .......................................................................................43 7.8 Analog Characteristics .....................................................................................44 7.9 Timing Characteristics .....................................................................................53 AT32UC3L0128/256 i ...
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... Mechanical Characteristics ................................................................... 63 9 Ordering Information ............................................................................. 68 10 Errata ....................................................................................................... 69 11 Datasheet Revision History .................................................................. 82 Table of Contents....................................................................................... i 32145AS–12/2011 8.1 Thermal Considerations ..................................................................................63 8.2 Package Drawings ...........................................................................................64 8.3 Soldering Profile ..............................................................................................67 10.1 Rev. C ..............................................................................................................69 10.2 Rev. B ..............................................................................................................71 10.3 Rev. A ..............................................................................................................75 11.1 Rev. A – 05/2010 .............................................................................................82 AT32UC3L0128/256 ii ...
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... Atmel , logo and combinations thereof, AVR Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL ...