AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 41

• Manufacturer Part Number: AT32UC3L0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.4
Table 7-14.
Notes:
32145AS–12/2011
Symbol
f
f
I
t
t
OUT
REF
DFLL
STARTUP
LOCK
1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively.
Digital Frequency Locked Loop (DFLL) Characteristics
cess technology. These values are not covered by test limits in production.
Digital Frequency Locked Loop Characteristics
Parameter
Output frequency
Reference frequency
FINE resolution step
Frequency drift over voltage
and temperature
Accuracy
Power consumption
Startup time
Lock time
(2)
(2)
(2)
(2)
Conditions
FINE > 100, all COARSE values
Open loop mode
FINE lock, f
ACCURATE lock, f
RCSYS/2, SSG disabled
FINE lock, f
disabled
ACCURATE lock, f
dither clk RCSYS/2, SSG disabled
Within 90% of final values
f
f
clock = RCSYS/2, SSG disabled
REF
REF
= 32kHz, ACCURATE lock, dithering
= 32kHz, FINE lock, SSG disabled
REF
REF
= 8-150kHz, SSG
= 32kHz, SSG disabled
REF
REF
= 32kHz, dither clk
= 8-150kHz,
(3)
Min
AT32UC3L0128/256
20
8
Figure 7-4
0.38
0.06
Typ
See
0.1
0.2
0.1
25
28
8
Max
150
150
100
0.5
0.5
1
1
µA/MHz
Unit
MHz
kHz
ms
µs
%
%
41