AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet
AT32UC3L0128
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AT32UC3L0128 Summary of contents
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... Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – SPI Slaves can be Addressed ® ® AVR Microcontroller 32-bit Atmel AVR Microcontroller AT32UC3L0256 AT32UC3L0128 32145A–12/2011 ...
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... Single-pin Programming Trace and Debug Interface Muxed with Reset Pin – NanoTrace Provides Trace Capabilities through JTAG or aWire Interface • 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) • Five High-drive I/O Pins • Single 1.62-3.6 V Power Supply 32145A–12/2011 2 C-compatible ® ® ® ® QTouch and Atmel AVR QMatrix Touch Acquisition AT32UC3L0128/256 2 ...
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... The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L0128/256 incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. ...
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... Suppression QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The AT32UC3L0128/256 integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System, with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic run- time control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers ...
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... OSC32K XOUT32 OSC0 DFLL PLL INTERRUPT CONTROLLER EXTERNAL INTERRUPT EXTINT[5..1] CONTROLLER NMI PWM CONTROLLER PWMA[35..0] ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER AT32UC3L0128/256 LOCAL BUS LOCAL BUS INTERFACE AVR32UC CPU 32 KB SRAM DATA INTERFACE M S 128/256 KB FLASH REGISTERS BUS PERIPHERAL DMA ...
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... AT32UC3L0256 256KB Digital Frequency Locked Loop 20-150 MHz (DFLL) Phase Locked Loop 40-240 MHz (PLL) Crystal Oscillator 0.45-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) RC Oscillator 32 kHz (RC32K) TQFP48/QFN48/TLLGA48 AT32UC3L0128/256 AT32UC3L0128 128KB 32KB ...
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... The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32145A–12/2011 TQFP48/QFN48 Pinout AT32UC3L0128/256 Section 3.2. 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND 18 VDDCORE 17 VDDIN 16 PB01 15 PA07 14 PA01 13 PA02 7 ...
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... USART0 USART1 SPI TXD RTS NPCS[2] USART0 USART1 SPI USART1 RXD CTS NPCS[3] CLK AT32UC3L0128/256 GPIO Function E F PWMA PWMA[0] GCLK[0] PWMA ACIFB TWIMS0 PWMA[1] ACAP[0] TWALM PA21 PB10 RESET_N ...
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... SPI TC0 TXD ADP[0] NPCS[0] A1 USART3 ADCIFB SPI TC0 RXD ADP[1] SCK B1 USART3 USART3 SPI TC0 RTS CLK MISO A2 AT32UC3L0128/256 PWMA ACIFB USART0 PWMA[2] ACBP[0] CLK PWMA ACIFB USART0 PWMA[3] ACBN[3] CLK PWMA ACIFB PWMA[4] ACBP[1] PWMA ACIFB TWIMS0 PWMA[5] ACBN[0] ...
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... CLK0 TXD CLK TC1 USART1 CLK1 RXD TC1 TWIMS1 CLK2 TWALM for a description of the various peripheral signals. ”Electrical Characteristics” on page 791 ”TWI Pin Characteristics(1)” on page 798 AT32UC3L0128/256 TC0 PWMA ACIFB B2 PWMA[26] ACBP[2] TWIMS0 PWMA PWMA TWALM PWMA[27] PWMAOD[27] TWIMS0 ...
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... JTAG debug port OSC0, OSC32 JTAG Pinout 48-pin Pin name 11 PA00 14 PA01 13 PA02 4 PA03 Nexus OCD AUX Port Connections AXS=1 AXS=0 PA05 PB08 PA10 PB00 PA18 PB04 PA17 PB05 PA16 PB03 PA15 PB02 PA14 PB09 AT32UC3L0128/256 JTAG pin TCK TMS TDO TDI 11 ...
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... PA20 Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA Section 6.1.4 on page 40 Other Functions 48-pin Pin 27 PA11 22 RESET_N 11 PA00 AT32UC3L0128/256 Oscillator Pin XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 for constraints on the WAKE_N pin. Function WAKE_N aWire DATA aWire DATAOUT ...
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... Analog Analog Analog ADC Interface - ADCIFB Analog Output Output Input aWire - AW I/O I/O Capacitive Touch Module - CAT I/O I/O Analog Output Input Output External Interrupt Controller - EIC Input Input Glue Logic Controller - GLOC Input Output JTAG module - JTAG Input Input Output AT32UC3L0128/256 Active Level Comments 13 ...
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... System Control Interface - SCIF Output Input Output Analog/ Digital Analog/ Digital Analog/ Digital Analog Analog Analog Serial Peripheral Interface - SPI I/O I/O I/O I/O Timer/Counter - TC0, TC1 I/O I/O I/O I/O I/O I/O Input Input Input Two-wire Interface - TWIMS0, TWIMS1 I/O I/O AT32UC3L0128/256 Low Not all channels support open drain mode Low Low 14 ...
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... Power Input Power Input Power Input Power Input Ground Ground Auxiliary Port - AUX Output Output Output Input Low Output Low General Purpose I/O pin I/O I/O AT32UC3L0128/256 Comments 1.62V to 1.98V 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. 1.62V to 1.98V 1.62V to 1.98V (1) 1.62V to 3.6V 15 ...
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... GPIO pins. Selected pins are also SMBus compliant (refer to Section 3.2 on page path to ground when the AT32UC3L0128/256 is powered down. This allows other devices on the SMBus to continue communicating even though the AT32UC3L0128/256 is not powered. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details ...
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... ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 32145A–12/2011 AT32UC3L0128/256 17 ...
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... Another feature of the instruction set is that frequently used instructions, like add, have a com- pact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a 32145A–12/2011 AT32UC3L0128/256 18 ...
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... Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 20 32145A–12/2011 displays the contents of AVR32UC. AT32UC3L0128/256 19 ...
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... Figure 4-2 on page 21 32145A–12/2011 Overview of the AVR32UC CPU OCD system AVR32UC CPU pipeline High Speed High Speed Bus master shows an overview of the AVR32UC pipeline stages. AT32UC3L0128/256 Power/ Reset control MPU Data memory controller High CPU Local Speed Bus ...
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... AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an 32145A–12/2011 The AVR32UC Pipeline Regfile IF ID Read Prefetch unit Decode unit AT32UC3L0128/256 MUL Multiply unit Regfile ALU ALU unit write Load-store LS unit ...
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... The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision binary-compatible with revision 3 CPUs. 32145A–12/2011 Instructions with Unaligned Reference Support Supported Alignment Word Word AT32UC3L0128/256 22 ...
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... SR 4-5. The lower word contains the and Q condition code flags and the R, T, The Status Register High Halfword - - - AT32UC3L0128/256 INT2 INT3 Exception Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit SP_SYS SP_SYS SP_SYS ...
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... Overview of Execution Modes, their Priorities and Privilege Levels. Mode Security Non Maskable Interrupt Privileged Exception Privileged Interrupt 3 Privileged Interrupt 2 Privileged Interrupt 1 Privileged Interrupt 0 Privileged Supervisor Privileged Application Unprivileged AT32UC3L0128/256 Bit Bit name Initial value Carry Zero Sign ...
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... Return Status Register for Debug mode 52 RAR_SUP Unused in AVR32UC 56 RAR_INT0 Unused in AVR32UC 60 RAR_INT1 Unused in AVR32UC 64 RAR_INT2 Unused in AVR32UC 68 RAR_INT3 Unused in AVR32UC 72 RAR_EX Unused in AVR32UC 76 RAR_NMI Unused in AVR32UC 80 RAR_DBG Return Address Register for Debug mode 84 JECR Unused in AVR32UC 88 JOSP Unused in AVR32UC 92 JAVA_LV0 Unused in AVR32UC AT32UC3L0128/256 25 ...
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... MPU Address Register region 3 336 MPUAR4 MPU Address Register region 4 340 MPUAR5 MPU Address Register region 5 344 MPUAR6 MPU Address Register region 6 348 MPUAR7 MPU Address Register region 7 352 MPUPSR0 MPU Privilege Select Register region 0 356 MPUPSR1 MPU Privilege Select Register region 1 AT32UC3L0128/256 26 ...
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... Secure State Stack Pointer System Register 436 SS_SP_APP Secure State Stack Pointer Application Register 440 SS_RAR Secure State Return Address Register 444 SS_RSR Secure State Return Status Register 448-764 Reserved Reserved for future use 768-1020 IMPL IMPLEMENTATION DEFINED Table 4-4 on page AT32UC3L0128/256 31. Most of the handlers are 27 ...
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... R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 32145A–12/2011 31, is loaded into the Program Counter. AT32UC3L0128/256 Table 4 ...
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... If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 32145A–12/2011 Table 4-4 on page 31. If events occur on several instructions at different AT32UC3L0128/256 29 ...
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... An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating- point unit. 32145A–12/2011 AT32UC3L0128/256 Table 4-4 on page 31. Some of 30 ...
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... MPU DTLB Miss (Write) MPU DTLB Protection (Read) MPU DTLB Protection (Write) MPU DTLB Modified UNUSED AT32UC3L0128/256 Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction ...
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... Sector lock capabilities, bootloader protection, security bit • 32 fuses, erased during chip erase • User page for data to be preserved during chip erase AT32UC3L0128/256 Physical Memory Map Start Address 0x00000000 0x80000000 ...
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... General-Purpose Input/Output Controller - GPIO Universal Synchronous Asynchronous Receiver USART0 Transmitter - USART0 Universal Synchronous Asynchronous Receiver USART1 Transmitter - USART1 Universal Synchronous Asynchronous Receiver USART2 Transmitter - USART2 Universal Synchronous Asynchronous Receiver USART3 Transmitter - USART3 SPI Serial Peripheral Interface - SPI TWIM0 Two-wire Master Interface - TWIM0 AT32UC3L0128/256 33 ...
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... Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 PWMA Pulse Width Modulation Controller - PWMA TC0 Timer/Counter - TC0 TC1 Timer/Counter - TC1 ADCIFB ADC Interface - ADCIFB ACIFB Analog Comparator Interface - ACIFB CAT Capacitive Touch Module - CAT GLOC Glue Logic Controller - GLOC AW aWire - AW AT32UC3L0128/256 34 ...
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... Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3L0128/256 Local Bus Mode Address Access WRITE 0x40000040 Write-only ...
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... Voltage Regulator The AT32UC3L0128/256 embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load 60mA. The regulator supplies the output voltage on VDDCORE. The regula- tor may only be used to drive internal circuitry in the device. VDDCORE should be externally connected to the 1.8V domains. See Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations ...
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... All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 1.98-3.6V VDDCORE 32145A–12/2011 Figure 6-2 3.3V Single Supply Mode + - VDDIN I/O Pins OSC32K_2, AST, Wake, Regulator regulator VDDANA AT32UC3L0128/256 shows the power schematics to be used for 3.3V VDDIO I/O Pins OSC32K, RC32K, POR33, control SM33 Linear CPU, Peripherals, Memories, SCIF, BOD, RCSYS, ADC ...
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... V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.98-3.6V 32145A–12/2011 1.8V Single Supply Mode VDDIN OSC32K_2, AST, Wake, Regulator VDDCORE VDDANA AT32UC3L0128/256 Figure 6-3. All I/O lines will be powered by the VDDIO I/O Pins I/O Pins OSC32K, RC32K, POR33, control SM33 CPU, Peripherals, Memories, ...
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... Supply Mode with 1.8V Regulated I/O Lines + - VDDIN OSC32K_2, AST, Wake, Regulator VDDCORE regulator VDDANA Section 3.2 on page 8 for description of power supply for each I/O line. AT32UC3L0128/256 Figure 6-4. This configuration is required in order to VDDIO I/O Pins I/O Pins OSC32K, RC32K, POR33, control SM33 Linear CPU, ...
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... A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V. • A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V. 6.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3L0128/256. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 ...
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... The PDCA communicates with the peripheral modules over a set of handshake interfaces. The peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowl- edges the request when the transmission has started. When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be generated. 32145A–12/2011 AT32UC3L0128/256 41 ...
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... The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA interrupts requires the interrupt controller to be programmed first. 32145A–12/2011 PDCA Block Diagram Memory HSB to PB HSB Bridge HSB HSB Peripheral DMA Controller (PDCA) IRQ Interrupt AT32UC3L0128/256 Peripheral 0 Peripheral 1 Peripheral 2 Peripheral (n-1) Handshake Interfaces 42 ...
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... MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value. After reload, the MARR and TCRR registers are cleared. 32145A–12/2011 AT32UC3L0128/256 Section 7.5.6. Section Section 7 ...
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... The current status of an interrupt source can be read through the Interrupt Status Register (ISR). The PDCA has three interrupt sources: • Reload Counter Zero - The TCRR register is zero. • Transfer Finished - Both the TCR and TCRR registers are zero. • Transfer Error - An error has occurred in accessing memory. 32145A–12/2011 AT32UC3L0128/256 44 ...
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... PWSTALL0/ channel, all registers in the channel are reset. This behavior is altered if the Channel Overflow Freeze bit is one in the Performance Control register (PCON- TROL.CH0/1OVF). If this bit is one, the channel registers are frozen when either DATA or STALL reaches its maximum value. This simplifies one-shot readout of the counter values. 32145A–12/2011 AT32UC3L0128/256 45 ...
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... PWLAT0/1) are saturating when their maximum count value is reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor- responding reset bit in PCONTROL (PCONTROL.CH0/1RES). A counter is enabled by writing a one to the Channel Enable bit in the Performance Control Reg- ister (PCONTROL.CH0/1EN). 32145A–12/2011 AT32UC3L0128/256 46 ...
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... Register Register Name Control Register Mode Register Status Register 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. AT32UC3L0128/256 Contents ... Version register 7-1. Each channel has a set of configuration regis- Access MAR Read/Write ...
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... The number of performance monitors is device specific. If the device has only one perfor- mance monitor, the Channel1 registers are not available. Please refer to the Module Configuration section at the end of this chapter for the number of performance monitors on this device. Register Register Name AT32UC3L0128/256 Access PCONTROL Read/Write PRDATA0 Read-only ...
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... Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA. During transfer, MADDR will point to the next memory location to be read/written. 32145A–12/2011 MADDR[31:24 MADDR[23:16 MADDR[15: MADDR[7:0] AT32UC3L0128/256 ...
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... See the Module Configuration section of PDCA for details. The width of the PID field is device specific and dependent on the number of peripheral modules in the device. 32145A–12/2011 PID AT32UC3L0128/256 ...
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... Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done. 32145A–12/2011 TCV[15: TCV[7:0] AT32UC3L0128/256 ...
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... Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non- zero value. 32145A–12/2011 MARV[31:24 MARV[23:16 MARV[15: MARV[7:0] AT32UC3L0128/256 ...
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... Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared. 32145A–12/2011 TCRV[15: TCRV[7:0] AT32UC3L0128/256 ...
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... Writing a one to this bit will disable transfer for the DMA channel. • TEN: Transfer Enable Writing a zero to this bit has no effect. Writing a one to this bit will enable transfer for the DMA channel. 32145A–12/2011 AT32UC3L0128/256 ECLR TDIS TEN 54 ...
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... SIZE: Size of Transfer Table 7-5. Size of Transfer SIZE Size of Transfer 0 Byte 1 Halfword 2 Word 3 Reserved 32145A–12/2011 RING AT32UC3L0128/256 ETRIG SIZE 55 ...
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... This bit is cleared when the TDIS bit written to one. This bit is set when the TEN bit written to one. 0: Transfer is disabled for the DMA channel. 1: Transfer is enabled for the DMA channel. 32145A–12/2011 AT32UC3L0128/256 TEN 56 ...
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... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32145A–12/2011 AT32UC3L0128/256 TERR TRC RCZ 57 ...
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... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32145A–12/2011 AT32UC3L0128/256 TERR TRC RCZ 58 ...
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... A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 32145A–12/2011 AT32UC3L0128/256 TERR TRC RCZ 59 ...
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... This bit is set when both the TCR and the TCRR are zero. • RCZ: Reload Counter Zero This bit is cleared when the TCRR holds a non-zero value. This bit is set when TCRR is zero. 32145A–12/2011 AT32UC3L0128/256 TERR TRC RCZ 60 ...
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... Performance channel 1 is disabled. 1: Performance channel 1 is enabled. • CH0EN: Performance Channel 0 Enable 0: Performance channel 0 is disabled. 1: Performance channel 0 is enabled. 32145A–12/2011 CH1OF CH0OF - AT32UC3L0128/256 26 25 MON1CH 18 17 MON0CH CH1RES CH1EN CH0RES 0 CH0EN 61 ...
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... Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L0128/256 ...
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... LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32145A–12/2011 LAT[15: LAT[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L0128/256 ...
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... LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32145A–12/2011 LAT[15: LAT[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L0128/256 ...
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... LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32145A–12/2011 LAT[15: LAT[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 DATA[31:24 DATA[23:16 DATA[15: DATA[7:0] AT32UC3L0128/256 ...
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... Reset Value: 0x00000000 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32145A–12/2011 STALL[31:24 STALL[23:16 STALL[15: STALL[7:0] AT32UC3L0128/256 ...
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... LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32145A–12/2011 LAT[15: LAT[7:0] AT32UC3L0128/256 ...
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... Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32145A–12/2011 VERSION[7:0] AT32UC3L0128/256 VARIANT VERSION[11: ...
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... PDCA Clocks Description Clock for the PDCA HSB interface Clock for the PDCA PB interface Register Reset Values Reset Value 123 Peripheral Identity Values Direction Peripheral Instance RX USART0 RX USART1 RX USART2 AT32UC3L0128/256 Peripheral Register RHR RHR RHR 75 ...
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... TWIM0 RX TWIM1 RX TWIS0 RX TWIS1 RX ADCIFB CAT TX USART0 TX USART1 TX USART2 TX USART3 TX SPI TX TWIM0 TX TWIM1 TX TWIS0 TX TWIS1 CAT AT32UC3L0128/256 Peripheral Register RHR RDR RHR RHR RHR RHR LCDR RHR ACOUNT THR THR THR THR TDR THR THR THR THR THR MBLEN 76 ...
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... FLASHCDW configuration and control registers. Failing may deadlock the bus. 8.3.3 Interrupts The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the FLASHCDW interrupts requires the interrupt controller to be programmed first. 32145A–12/2011 AT32UC3L0128/256 77 ...
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... Wait state support and a read granularity of 64 bits ensure efficiency in such systems. Performance for systems with high clock frequency is increased since the internal read word width of the flash memory is 64 bits. When a 32-bit word addressed, the word itself and 32145A–12/2011 AT32UC3L0128/256 Figure 8-1 on page 80. 78 ...
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... The User page is permanently mapped to an offset of 0x00800000 from the start address of the flash memory. Table 8-1. Memory type Main array User 32145A–12/2011 User Page Addresses Start address, byte sized 0 0x00800000 AT32UC3L0128/256 Figure 8-1. The memory space between Size pw bytes w bytes 79 ...
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... Normal and High Speed Read Mode. 32145A–12/2011 Memory Map for the Flash Memories Offset from base address 0x0080 0000 pw 0 Flash with User Page All addresses are byte addresses AT32UC3L0128/256 Reserved User Page Flash base address 80 ...
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... A%32 in the page buffer. The PAGEN field in the Flash Command (FCMD) register will at the same time be updated with the value A/32. 32145A–12/2011 High Speed Mode Frequency AT32UC3L0128/256 1 wait state 0 wait state Frequency limit for 0 wait state ...
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... Page Buffer 64-bit data AT32UC3L0128/256 Flash Z31 Z30 Z29 Z28 Z27 Z26 Z25 Z24 Z23 Z22 Z21 Z20 Z19 Z18 Z17 Z16 Page Z Z15 Z14 Z13 Z12 Z11 Z10 Z9 ...
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... Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the Erase Page command. The User page can be written and erased using the mechanisms described in this chapter. 32145A–12/2011 AT32UC3L0128/256 Section 8.8.2 for a complete list of 83 ...
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... When the command is complete, the FRDY bit in the Flash Status Register (FSR) is set interrupt has been enabled by writing FCR.FRDY to one, an interrupt request is generated. Two errors can be detected in the FSR register after issuing the command: 32145A–12/2011 executed to unlock the corresponding region before programming can start. privileges. AT32UC3L0128/256 Section 8.4.8 on page 81. 84 ...
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... The flash memory has a number of general-purpose fuse bits that the application programmer can use freely. The fuse bits can be written and erased using dedicated commands, and read 32145A–12/2011 Section 8.6. The general-purpose bit being in an erased (1) state means that the region 8.6. AT32UC3L0128/256 85 ...
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... If programmed (i.e. “0”), the JTAG USER PROTECTION feature is enabled. If this fuse is programmed some HSB addresses will be accessible by JTAG access even if the flash UPROT security fuse is programmed. Refer to the JTAG documentation for more information on this functionality. This bit can only be changed when the security bit is cleared. AT32UC3L0128/256 86 ...
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... Secure State Configuration Functionality Secure state disabled Secure enabled, secure state debug enabled Secure enabled, secure state debug disabled Secure state disabled while the flash is locked by the security bit. enabled. Section 8.5.3. AT32UC3L0128/256 SSE SSDE ...
Page 88
... Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2 • Erase All General-Purpose Fuses (EAGPF) One error can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. 32145A–12/2011 AT32UC3L0128/256 Chip or aWire 88 ...
Page 89
... All bits in FGPRHI/LO are dependent on the programmed state of the fuses they map to. Any bits in these registers not mapped to a fuse read The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 32145A–12/2011 Register Register Name AT32UC3L0128/256 Access FCR Read/Write FCMD Read/Write FSR ...
Page 90
... Lock Error generates an interrupt request. • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt request. 1: Flash Ready generates an interrupt request. 32145A–12/2011 PROGE AT32UC3L0128/256 BRBUF SEQBUF - LOCKE - FRDY 90 ...
Page 91
... PAGEN [15: PAGEN [7: PAGEN description Not used The number of the page to write Not used Page number whose region should be locked Page number whose region should be unlocked Not used GPFUSE # GPFUSE # Not used AT32UC3L0128/256 CMD ...
Page 92
... PAGEN description WriteData[7:0], ByteAddress[2:0] Not used Page number Not used Not used Not used Not used Not used Value Mnemonic 0 NOP CPB WGPB 8 EGPB 9 SSB 10 PGPFB 11 EAGPF 12 QPR 13 WUP 14 EUP 15 QPRUP 16 HSEN 17 HSDIS 16-31 AT32UC3L0128/256 92 ...
Page 93
... The Flash Controller is busy and the application must wait before running a new command. 1: The Flash Controller is ready to run a new command. 32145A–12/2011 LOCK13 LOCK12 LOCK11 LOCK5 LOCK4 LOCK3 QPRR SECURITY PROGE AT32UC3L0128/256 LOCK10 LOCK9 LOCK8 LOCK2 LOCK1 LOCK0 LOCKE - FRDY 93 ...
Page 94
... The size of each flash page. Table 8-9. Flash Page Size PSZ Page Size 0 32 Byte 1 64 Byte 2 128 Byte 3 256 Byte 4 512 Byte 5 1024 Byte 6 2048 Byte 7 4096 Byte 32145A–12/2011 AT32UC3L0128/256 PSZ FSZ 94 ...
Page 95
... Flash Size FSZ 0 4 Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte 14 7 128 Kbyte 15 32145A–12/2011 Flash Size 192 Kbyte 256 Kbyte 384 Kbyte 512 Kbyte 768 Kbyte 1024 Kbyte 2048 Kbyte Reserved AT32UC3L0128/256 95 ...
Page 96
... VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32145A–12/2011 VERSION[7:0] AT32UC3L0128/256 VARIANT VERSION[11: ...
Page 97
... The fuse has an erased state. 32145A–12/2011 GPF61 GPF60 GPF59 GPF53 GPF52 GPF51 GPF45 GPF44 GPF43 GPF37 GPF36 GPF35 AT32UC3L0128/256 GPF58 GPF57 GPF56 GPF50 GPF49 GPF48 GPF42 GPF41 GPF40 GPF34 GPF33 GPF32 97 ...
Page 98
... The fuse has an erased state. 32145A–12/2011 GPF29 GPF28 GPF27 GPF21 GPF20 GPF19 GPF13 GPF12 GPF11 GPF05 GPF04 GPF03 AT32UC3L0128/256 GPF26 GPF25 GPF24 GPF18 GPF17 GPF16 GPF10 GPF09 GPF08 GPF02 GPF01 GPF00 98 ...
Page 99
... Note that when writing to the user page the values do not get loaded by the other modules on the device until a chip reset occurs. The general purpose fuses are erased by a JTAG or aWire chip erase. 32145A–12/2011 AT32UC3L0128/256 99 ...
Page 100
... LOCK fuses set to 1111111111111111. No region locked. After the JTAG or aWire chip erase command, the FGPFR register value is 0xFFFFFFFF. 32145A–12/2011 29 28 BODHYST 21 20 SECURE 13 12 LOCK[15: LOCK[7:0] AT32UC3L0128/256 BODLEVEL[5: BOOTPROT ”Electrical Characteristics” on page ...
Page 101
... Default user page first word value The devices are shipped with the user page erased (all bits 1): • WDTAUTO set to 1, WDT disabled. 32145A–12/2011 AT32UC3L0128/256 WDTAUTO 101 ...
Page 102
... SSADRF[15: SSADRF[7:0] Module Configuration AT32UC3L0256 256Kbytes 512 512bytes Module Clock Name Clock Name CLK_FLASHCDW_HSB CLK_FLASHCDW_PB AT32UC3L0128/256 AT32UC3L0128 128Kbytes 256 512bytes Description Clock for the FLASHCDW HSB interface Clock for the FLASHCDW PB interface 102 ...
Page 103
... Table 8-13. Register FVR FPR 32145A–12/2011 Register Reset Values AT32UC3L0256 0x00000120 0x00000409 AT32UC3L0128/256 AT32UC3L0128 0x00000120 0x00000407 103 ...
Page 104
... Only one channel can be open at a time, opening a channel while another one is open locks the first one • Access to a locked channel is denied, a bus error and optionally an interrupt is returned • channel is relocked due to an unlock timeout, an interrupt can optionally be generated AT32UC3L0128/256 104 ...
Page 105
... SAU. The CPU wants to Figure 9-1. SAU Block Diagram CPU MPU Bus master Bus slave Bus slave Bus master SAU Channel SAU Configuration SAU AT32UC3L0128/256 Flash RAM Bus slave High Speed Bus Bus slave Bus bridge USART PWM 105 ...
Page 106
... PB register. When all channels have been configured, return to normal mode by writing a one to the Setup Mode Disable (SDIS) in CR. The channels can now be enabled by writing ones to the corresponding bits in the Channel Enable Registers (CERH/L). The SAU is only able to remap addresses above 0xFFFC0000. 32145A–12/2011 AT32UC3L0128/256 106 ...
Page 107
... To confirm that the access was successful, wait for the IDLE transfer status bit (SR.IDLE) to indicate the operation is completed. Then check SR for possible error con- ditions. The SAU can be configured to generate interrupt requests or a Bus Error Exception if the access failed. 32145A–12/2011 AT32UC3L0128/256 107 ...
Page 108
... Example Memory Map for a System with SAU Receive Holding SAU Transmit Holding CONFIG UART SAU CHANNEL AT32UC3L0128/256 Address X Baudrate Control UR RTR62 Channel 1 RTR1 RTR0 Address Z Section 9.5.7 108 ...
Page 109
... To disable the SAU, the user must first ensure that no SAU bus operations are pending. This can be done by checking that the SR.IDLE bit is set. The SAU may then be disabled by writing a one to the Disable (DIS) bit in CR. 32145A–12/2011 AT32UC3L0128/256 Section 9.5.6). 109 ...
Page 110
... Remap Target Register n 0xFC 32145A–12/2011 Register Control Register Configuration Register Status Register Interrupt Mask Register Interrupt Clear Register Parameter Register Version Register Register ... Unlock Register AT32UC3L0128/256 Register Name Access CR Write-only 0x00000000 CONFIG Write-only 0x00000000 CERH Read/Write 0x00000000 CERL Read/Write ...
Page 111
... Writing a one to this bit disables the SAU. • EN: SAU Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the SAU. 32145A–12/2011 BERREN SDIS AT32UC3L0128/256 SEN DIS EN 111 ...
Page 112
... Once a channel has been unlocked, it remains unlocked for this amount of CLK_SAU_HSB clock cycles or until one access to a channel has been made. • UKEY: Unlock Key The value in this field must be written to UR.KEY to unlock a channel. 32145A–12/2011 UCYC UKEY AT32UC3L0128/256 OPEN 112 ...
Page 113
... Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is enabled. 32145A–12/2011 CERH[30:24 CERH[23:16 CERH[15: CERH[7:0] AT32UC3L0128/256 113 ...
Page 114
... Offset: 0x0C Reset Value: 0x00000000 • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled. 32145A–12/2011 CERL[31:24 CERL[23:16 CERL[15: CERL[7:0] AT32UC3L0128/256 114 ...
Page 115
... This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if the Unlock Register was read. 32145A–12/2011 URES URKEY URREAD AT32UC3L0128/256 IDLE SEN CAU CAS EXP 115 ...
Page 116
... This bit is set if channel access successful, i.e. one access was made after the channel was unlocked. • EXP: Channel Unlock Expired This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel unlock has expired, i.e. no access being made after the channel was unlocked. 32145A–12/2011 AT32UC3L0128/256 116 ...
Page 117
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32145A–12/2011 URES URKEY URREAD AT32UC3L0128/256 CAU CAS EXP 117 ...
Page 118
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32145A–12/2011 URES URKEY URREAD AT32UC3L0128/256 CAU CAS EXP 118 ...
Page 119
... A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 32145A–12/2011 URES URKEY URREAD AT32UC3L0128/256 CAU CAS EXP 119 ...
Page 120
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and any corresponding interrupt request. 32145A–12/2011 URES URKEY URREAD AT32UC3L0128/256 CAU CAS EXP 120 ...
Page 121
... Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x24 Reset Value • CHANNELS: Number of channels implemented. 32145A–12/2011 CHANNELS AT32UC3L0128/256 121 ...
Page 122
... Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32145A–12/2011 VERSION[7:0] AT32UC3L0128/256 VARIANT VERSION[11: 122 ...
Page 123
... RTR[31:16] must have one of the following values, any other value will result in UNDEFINED behavior: 0xFFFC 0xFFFD 0xFFFE 0xFFFF RTR[1:0] must be written to 00, any other value will result in UNDEFINED behavior. 32145A–12/2011 RTR[31:24 RTR[23:16 RTR[15: RTR[7:0] AT32UC3L0128/256 123 ...
Page 124
... The correct key must be written in order to unlock a channel. The key value written must correspond to the key value defined in CONFIG.UKEY. • CHANNEL: Channel Number Number of the channel to unlock. 32145A–12/2011 KEY AT32UC3L0128/256 CHANNEL 124 ...
Page 125
... Module name SAU SAU Table 9-5. Register VERSION PARAMETER 32145A–12/2011 SAU configuration SAU 16 SAU clock name Clock name Description CLK_SAU_HSB Clock for the SAU HSB interface CLK_SAU_PB Clock for the SAU PB interface Register Reset Values Reset Value 0x00000111 0x00000010 AT32UC3L0128/256 125 ...
Page 126
... This bus granting mechanism sets a different default master for every slave. At the end of the current access other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master, and fixed default master. 32145A–12/2011 AT32UC3L0128/256 126 ...
Page 127
... This is described below. 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. This is described below. 32145A–12/2011 . AT32UC3L0128/256 “Arbitration 127 ...
Page 128
... Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the cur- 32145A–12/2011 AT32UC3L0128/256 128 ...
Page 129
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (PRAS and PRBS). 10.4.3 Slave and Master assignation The index number assigned to Bus Matrix slaves and masters are described in the Module Con- figuration section at the end of this chapter. 32145A–12/2011 AT32UC3L0128/256 129 ...
Page 130
... Slave Configuration Register 13 0x0078 Slave Configuration Register 14 0x007C Slave Configuration Register 15 0x0080 Priority Register A for Slave 0 0x0084 Priority Register B for Slave 0 0x0088 Priority Register A for Slave 1 32145A–12/2011 AT32UC3L0128/256 Name Access MCFG0 Read/Write MCFG1 Read/Write MCFG2 Read/Write MCFG3 Read/Write MCFG4 ...
Page 131
... Special Function Register 1 0x0118 Special Function Register 2 0x011C Special Function Register 3 0x0120 Special Function Register 4 0x0124 Special Function Register 5 0x0128 Special Function Register 6 32145A–12/2011 AT32UC3L0128/256 Name Access PRBS1 Read/Write PRAS2 Read/Write PRBS2 Read/Write PRAS3 Read/Write PRBS3 Read/Write PRAS4 ...
Page 132
... Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 Special Function Register 13 0x0148 Special Function Register 14 0x014C Special Function Register 15 32145A–12/2011 AT32UC3L0128/256 Name Access SFR7 Read/Write SFR8 Read/Write SFR9 Read/Write SFR10 Read/Write SFR11 Read/Write SFR12 ...
Page 133
... The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. AT32UC3L0128/256 – – ...
Page 134
... This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. 32145A–12/2011 – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT32UC3L0128/256 – – ARBT DEFMSTR_TYPE – – – 134 ...
Page 135
... MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32145A–12/2011 M7PR - M5PR - M3PR - M1PR - AT32UC3L0128/256 M6PR M4PR M2PR M0PR 135 ...
Page 136
... MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32145A–12/2011 M15PR - M13PR - M11PR - M9PR - AT32UC3L0128/256 M14PR M12PR M10PR M8PR 136 ...
Page 137
... SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 32145A–12/2011 SFR SFR SFR SFR AT32UC3L0128/256 137 ...
Page 138
... Slave 3 Slave 4 32145A–12/2011 HMATRIX Clocks Description Clock for the HMATRIX bus interface High Speed Bus Masters CPU Data CPU Instruction CPU SAB SAU PDCA High Speed Bus Slaves Internal Flash HSB-PB Bridge A HSB-PB Bridge B Internal SRAM SAU AT32UC3L0128/256 138 ...
Page 139
... Figure 10-1. HMatrix Master / Slave Connections 32145A–12/2011 HMATRIX SLAVES 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 SAU 3 PDCA 4 AT32UC3L0128/256 139 ...
Page 140
... The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure. 32145A–12/2011 gives an overview of the INTC. The grey boxes represent registers that can be AT32UC3L0128/256 140 ...
Page 141
... INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding 32145A–12/2011 Interrupt Controller ValReqN GrpReqN OR . IPRn . . IRRn . . Request . Masking ValReq1 GrpReq1 OR IPR1 IRR1 ValReq0 GrpReq0 OR IPR0 IRR0 IPR Registers IRR Registers AT32UC3L0128/256 Masks INT_level, offset . INTLEVEL . . INT_level, AUTOVECTOR offset INT_level, offset ICR Registers CPU SREG Masks I[3-0]M GM 141 ...
Page 142
... Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal. The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a 32145A–12/2011 AT32UC3L0128/256 142 ...
Page 143
... AT32UC3L0128/256 143 ...
Page 144
... Interrupt Cause Register 3 0x204 Interrupt Cause Register 2 0x208 Interrupt Cause Register 1 0x20C Interrupt Cause Register 0 32145A–12/2011 Register Name ... IPR63 IRR0 IRR1 ... IRR63 ICR3 ICR2 ICR1 ICR0 AT32UC3L0128/256 Access IPR0 Read/Write IPR1 Read/Write ... ... Read/Write Read-only Read-only ... ... Read-only Read-only Read-only Read-only Read-only Reset ...
Page 145
... AUTOVECTOR: Autovector Address Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment. 32145A–12/2011 AUTOVECTOR[13: AUTOVECTOR[7:0] AT32UC3L0128/256 145 ...
Page 146
... The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only. 32145A–12/2011 IRR[32*x+28] IRR[32*x+27 IRR[32*x+20] IRR[32*x+19 IRR[32*x+12] IRR[32*x+11 IRR[32*x+4] IRR[32*x+3] AT32UC3L0128/256 26 25 IRR[32*x+26] IRR[32*x+25] IRR[32*x+24 IRR[32*x+18] IRR[32*x+17] IRR[32*x+16 IRR[32*x+10] IRR[32*x+9] IRR[32*x+ IRR[32*x+2] IRR[32*x+1] IRR[32*x+ ...
Page 147
... ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending. 32145A–12/2011 AT32UC3L0128/256 CAUSE 147 ...
Page 148
... Peripheral DMA Controller 6 2 Peripheral DMA Controller 3 Peripheral DMA Controller 7 0 Power Manager 8 0 System Control Interface 9 0 Asynchronous Timer AT32UC3L0128/256 Description Clock for the INTC bus interface SYSREG COMPARE OCD DCEMU_DIRTY OCD DCCPU_READ FLASHCDW PDCA 0 PDCA 1 PDCA 2 PDCA 3 PDCA 4 PDCA 5 PDCA 6 PDCA 7 ...
Page 149
... Two-wire Slave Interface 24 0 Pulse Width Modulation Controller 0 Timer/Counter 25 1 Timer/Counter 2 Timer/Counter 0 Timer/Counter 26 1 Timer/Counter 2 Timer/Counter AT32UC3L0128/256 AST PER AST OVF AST READY AST CLKREADY EIC 1 EIC 2 EIC 3 EIC 4 EIC 5 FREQM GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 USART0 ...
Page 150
... Table 11-3. 32145A–12/2011 Interrupt Request Signal Map 27 0 ADC Interface 28 0 Analog Comparator Interface 29 0 Capacitive Touch Module 30 0 aWire AT32UC3L0128/256 ADCIFB ACIFB CAT AW 150 ...
Page 151
... Only a small amount of logic, including the 32KHz crystal oscillator (OSC32K) and the AST remain powered. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 32145A–12/2011 AT32UC3L0128/256 151 ...
Page 152
... PM interrupt requires the interrupt controller to be configured first. 12.5.2 Clock Implementation In AT32UC3L0128/256, the HSB shares source clock with the CPU. Write attempts to the HSB Clock Select register (HSBSEL) will be ignored, and it will always read the same as the CPU Clock Select register (CPUSEL). ...
Page 153
... CPU 32145A–12/2011 f . The synchronous clock source can be changed on- CPU PBx, Section 12.6.3. The module clocks in every synchronous clock domain Sleep Sleep Instruction Controller 0 Main Clock 1 CPUDIV CPUSEL (CPUSEL+ main AT32UC3L0128/256 Mask CPU Clocks HSB Clocks PBx Clocks CPUMASK 153 ...
Page 154
... When the CPU is idle possible to switch it and other (optional) clock domains off to save power. This is done by the sleep instruction, which takes the sleep mode index number from Table 12-2 on page 155 32145A–12/2011 (PBSEL+ argument. AT32UC3L0128/256 CPU < the Power Manager will automatically CPU PBx f CPU ...
Page 155
... Run Run Run Stop Run Run Stop Stop Run Stop Stop Run Stop Stop Run Stop Stop Run AT32UC3L0128/256 Table 12-2 on page (2) and RCSYS remain operational. (2) remains operational. This Section 12.6.4 BOD & Voltage (2) RCSYS Bandgap Regulator Run On Normal mode Run On Normal mode ...
Page 156
... DeepStop Asynchronous Static Asynchronous Shutdown External reset, External wake-up pin 1. The sleep mode index is used as argument for the sleep instruction. 2. Only PB modules operational, as HSB module clocks are stopped. 3. WDT only available if clocked from pre-enabled OSC32K. AT32UC3L0128/256 Table 12-3 on page , Asynchronous (3) 156. 156 ...
Page 157
... All modules should normally be disabled before entering Shutdown sleep mode (see 32145A–12/2011 I/O Lines Usage During Shutdown Mode Possible Usage During Shutdown Sleep Mode WAKE_N signal (active low wake-up) XIN32_2 (OSC32K using alternate pinout) XOUT32_2 (OSC32K using alternate pinout) Reset pin Section 12.6.3.5) AT32UC3L0128/256 Section 12.6.4. 157 ...
Page 158
... The device is kept under reset until RESET_N is tied high again OSC32K must be set-up to use alternate pinout (XIN32_2 and XOUT32_2) Refer to the SCIF Chapter AST must be configured to use the clock from OSC32K AST must be configured to allow alarm, periodic, or overflow wake-up AT32UC3L0128/256 Table 12-5. 158 ...
Page 159
... OCD Watchdog Reset Reset Description Description Supply voltage below the Power-on Reset detector threshold voltage V POT RESET_N pin asserted VDDCORE supply voltage below the Brown-out detector threshold voltage AT32UC3L0128/256 CPU, HSB, PBx OCD, AST, WDT, Reset Clock Generator Table 12-6 on page 159 ...
Page 160
... The PM has a number of interrupt sources: • Access Error, 32145A–12/2011 Description Internal regulator supply voltage below the SM33 threshold voltage. This generates a Power-on Reset. See Watchdog Timer documentation See On-Chip Debug documentation AT32UC3L0128/256 ). The POR will be re-generated POT ). The POT 160 ...
Page 161
... Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from the Power Manager will remain active until all the bits in ISR are cleared. 32145A–12/2011 zero-to-one transition on SR.CKRDY is detected). AT32UC3L0128/256 161 ...
Page 162
... CPUMASK HSB Mask HSBMASK PBA Mask PBAMASK PBB Mask PBBMASK Reserved PBADIVMASK Reserved CFDCTRL UNLOCK Reserved Reserved Reserved RCAUSE WCAUSE Reserved VERSION AT32UC3L0128/256 Access Read/Write CPUSEL Read/Write HSBSEL Read-only PBASEL Read/Write PBBSEL Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only IER ...
Page 163
... MCSEL: Main Clock Select Table 12-8. Main clocks in AT32UC3L0128/256. MCSEL[2:0] Main clock source 0 System RC oscillator (RCSYS) 1 Oscillator0 (OSC0) 2 120MHz RC oscillator 3 (RC120M) Note the 120MHz RC oscillator is selected as main clock source, it must be divided by at least 4 before being used as clock source for the CPU ...
Page 164
... Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32145A–12/2011 (CPUSEL+1) . AT32UC3L0128/256 CPUSEL 164 ...
Page 165
... HSBSEL Access Type: Read Offset: 0x008 Reset Value: 0x00000000 HSBDIV - This register is read-only and its content is always equal to CPUSEL. 32145A–12/2011 AT32UC3L0128/256 HSBSEL 165 ...
Page 166
... Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32145A–12/2011 (PBSEL+1) . AT32UC3L0128/256 PBSEL 166 ...
Page 167
... If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 12-9. Table 12-9. Maskable Module Clocks in AT32UC3L0128/256. Bit CPUMASK 0 OCD 1 ...
Page 168
... Table 12-9. Maskable Module Clocks in AT32UC3L0128/256. Bit CPUMASK SYSTIMER 31:26 - Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32145A–12/2011 ...
Page 169
... MASK[6:0] (n+1) is stopped. If bit n is written to one, the clock divided by 2 Table 12-10 shows what clocks are affected by the different MASK bits. USART2 USART3 - - - - CLK_USART/ CLK_USART/ DIV DIV - - - - - - - - AT32UC3L0128/256 (n+1) is enabled TC0 TC1 TIMER_CLOCK2 TIMER_CLOCK2 - - TIMER_CLOCK3 TIMER_CLOCK3 - - TIMER_CLOCK4 ...
Page 170
... Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32145A–12/2011 AT32UC3L0128/256 CFDEN 170 ...
Page 171
... KEY: Unlock Key Write this bit field to 0xAA to enable unlock. • ADDR: Unlock Address Write the address of the register to unlock to this field. 32145A–12/2011 KEY ADDR[7:0] AT32UC3L0128/256 ADDR[9: 171 ...
Page 172
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 172 ...
Page 173
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 173 ...
Page 174
... The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 174 ...
Page 175
... This bit is cleared when the corresponding bit in ICR is written to one. This bit is set on a zero-to-one transition of the corresponding bit in the Status Register (SR). 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 175 ...
Page 176
... Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR. 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 176 ...
Page 177
... The synchronous clocks have frequencies as indicated in the CPUSEL/PBxSEL registers. • CFD: Clock Failure Detected 0: Main clock is running correctly. 1: Failure on main clock detected. Main clock is now running on RCSYS. 32145A–12/2011 CKRDY - - AT32UC3L0128/256 CFD 177 ...
Page 178
... RC32 signal is not forced as output 1: RC32 signal is forced as output • RSTPUN: Reset Pull-up, active low 0: Pull-up for external reset on 1: Pull-up for external reset off 32145A–12/2011 PPC[31:24 PPC[23:16 PPC[15: PPC[7:0] AT32UC3L0128/256 178 ...
Page 179
... TWIS1RCMASK: TWIS1 Request Clock Mask 0: TWIS1 Request Clock is disabled 1: TWIS1 Request Clock is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32145A–12/2011 AT32UC3L0128/256 179 ...
Page 180
... POR33 detector), or the internal regulator supply voltage being lower than the minimum required input voltage (generated by the 3.3V supply monitor SM33). 32145A–12/2011 AWIRE - WDT AT32UC3L0128/256 JTAG OCDRST EXT BOD POR 180 ...
Page 181
... Table 12-12. Wake Cause Bit Wake Cause 0 CAT 1 ACIFB 2 ADCIFB 3 TWI Slave 0 4 TWI Slave 1 5 WAKE_N 6 ADCIFB Pen Detect 15 EIC 17 AST 31:18 - 32145A–12/2011 WCAUSE[31:24 WCAUSE[23:16 WCAUSE[15: WCAUSE[7:0] AT32UC3L0128/256 Table 12-12 on page 181 181 ...
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... The corresponding wake-up source is enabled Table 12-13. Asynchronous Wake-up Sources Bit Asynchronous Wake-up Source 0 CAT 1 ACIFB 2 ADCIFB 3 TWIS0 4 TWIS1 5 WAKEN 6 ADCIFBPD 31:7 - 32145A–12/2011 AWEN[31:24 AWEN[23:16 AWEN[15: AWEN[7:0] AT32UC3L0128/256 Table 12-13 on page 182. 182 ...
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... PBC implemented. • PBB: PBB Implemented 0: PBB not implemented. 1: PBB implemented. • PBA: PBA Implemented 0: PBA not implemented. 1: PBA implemented. 32145A–12/2011 PBD AT32UC3L0128/256 PBC PBB PBA 183 ...
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... Reset Value • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32145A–12/2011 VERSION[7:0] AT32UC3L0128/256 VARIANT VERSION[11: 184 ...
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... Reset Reset AT32UC3L0128/256 Reset Value 0x00000420 BOD SM33 CPU Error Reset Reset Reset ...
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... Pin Description RC32 output at startup Crystal 0 Input Crystal 32 Input (primary location) Crystal 32 Input (secondary location) Crystal 0 Output Crystal 32 Output (primary location) Crystal 32 Output (secondary location) Generic Clock Output Generic Clock Input AT32UC3L0128/256 Type Output Analog/Digital Analog/Digital Analog/Digital Analog Analog Analog Output ...
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... I/O. The oscillator is enabled by writing a one to the Oscillator Enable bit in the Oscillator Control reg- ister (OSCCTRLn.OSCEN). Operation mode (external clock or crystal) is selected by writing to the Oscillator Mode bit in OSCCTRLn (OSCCTRLn.MODE). The oscillator is automatically dis- 32145A–12/2011 AT32UC3L0128/256 187 ...
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... Enable 32KHz output bit in the OSCCTRL32 register (OSCCTRL32.EN32K). OSCCTRL32.EN32K is set after a POR. The 32 KHz oscillator has two possible sets of pins. To select between them write to the Pin Select bit in the OSCCTRL32 register (OSCCTRL32.PINSEL). If the 32KHz oscillator 32145A–12/2011 AT32UC3L0128/256 188 ...
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... The PLL Multiply Factor (PLLMUL) and PLL Division 32145A–12/2011 PLLMUL f Output vco Divider 1/2 Phase VCO Detector Counter PLLOPT[0] AT32UC3L0128/256 PLLOPT[1] f PLL 0 Mask PLL clock 1 Lock Lock bit PLL Oscillator Select field ( PLLOSC) 189 ...
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... To prevent unexpected writes due to software bugs, write access to the configuration registers is protected by a locking mechanism. For details please refer to the UNLOCK register description. 32145A–12/2011 = (PLLMUL+1)/PLLDIV • PLLDIV >0 REF = 2•(PLLMUL+1) • PLLDIV = 0 REF AT32UC3L0128/256 190 ...
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... Coarse Calibration Value field (COARSE) and the Fine Calibration Value field (FINE) in the DFLLnCONF register. When writing to COARSE and 32145A–12/2011 COARSE FINE CSTEP FSTEP FREQUENCY 8+9 TUNER IMUL FMUL 32 DFLLLOCKF DFLLLOCKLOSTF DFLLLOCKC DFLLLOCKA DFLLLOCKLOSTC DFLLLOCKLOSTA AT32UC3L0128/256 8 DFLL 9 CLK_DFLLIF_DITHER CLK_DFLLIF_REF 191 ...
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... FINE bits to obtain an accurate average output frequency. DFLLn Locked on Accurate Value bit (DFLLnLOCKA) in PCLKSR will be set when this is done. The ACCURATE stage will 32145A–12/2011 ) is given by: DFLL f = DFLL is the frequency of CLK_DFLLIF_REF. COARSE and FINE in DFLLnCONF are read- REF AT32UC3L0128/256 Section 13.5.4.5. When a lock FMUL ⎛ ⎞ f IMUL + ---------------- - ⎝ ...
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... For lock times, please refer to the Electrical Characteristics chapter. 32145A–12/2011 Measure f DFLLn DFLLnLOCKC 1 DFLLnLOCKF Calculate Calculate new new FINE COARSE value value Target frequency Initial frequency DFLLnLOCKC DFLLnLOCKF DFLLnLOCKA AT32UC3L0128/256 Compen- DITHER 1 DFLLnLOCKA 1 sate for drift 0 0 Calculate Compen- new sate for dithering drift dutycycle 193 ...
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... When the DFLL is used as the main clock source for the device, the EMI radiated from the device will be synchronous to f 32145A–12/2011 error NUMREF is the number of reference clock cycles the DFLLIF is using for calculating the provide better Electromagnetic Compatibility (EMC) the DFLL AT32UC3L0128/256 without losing either of the DFLL RATIODIFF f REF = ------------------------------------------------ - NUMREF f ...
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... Accuracy There are mainly three factors that decide the accuracy of the f obtain maximum accuracy when fine lock is achieved. 32145A–12/2011 . DFLL Pseudorandom CLK_DFLLIF_DITHER Binary Sequence AT32UC3L0128/256 to ensure that the DFLLIF REF FINE 1 Spread Spectrum Generator 0 AMPLITUDE, PRBS STEPSIZE ...
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... After enabling the BOD, the BOD output will be masked during one half of a RCSYS clock cycle and two main clocks cycles to avoid false results. When the JTAG or aWire is enabled, the BOD reset and interrupt are masked. 32145A–12/2011 AT32UC3L0128/256 is low, i.e. the ratio DFLL 196 ...
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... The Bandgap reference is powered by the internal regulator supply voltage and will not be powered during Shutdown sleep mode. Please refer to the Power Manager chapter for details. 32145A–12/2011 AT32UC3L0128/256 VDDCORE POR18 POWER MANAGER(PM) BOD ...
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... The default value of this field corresponds to a regulator output voltage of 1.8V. Other values of this field are not defined, and it is not recommended to change the value of this field. The Voltage Regulator OK bit (VREGCR.VREGOK) bit indicates when the voltage regulator out- put has reached the voltage threshold level. 32145A–12/2011 AT32UC3L0128/256 198 ...
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... Writing a zero to VREGCR.POR18EN bit will have no effect. To avoid spurious resets mandatory to mask the Power-on Reset when enabling or dis- abling the POR18 detector. The Power-on Reset generated by the POR18 detector can be ignored by writing a one to the POR18 Mask bit (VREGCR.POR18MASK). Because of internal 32145A–12/2011 AT32UC3L0128/256 199 ...
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... If the SM33 is enabled (SM33.CTRL is one or two) and the regulator supply voltage drops below the SM33 threshold, the SM33DET bit in the Power and Clocks Status Register (PCLKSR.SM33DET) is set. This bit is cleared when the supply voltage goes above the thresh- old. An interrupt request is generated on a zer-to-one transition of PCLKSR.SM33DET if the 32145A–12/2011 AT32UC3L0128/256 200 ...