AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 11

• Manufacturer Part Number: AT89C51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89C51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 2
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Table 15. Pin Description
11
V
V
P0.0 - P0.7
P1.0 - P1.7
SS
CC
Mnemonic
AT89C51ID2
PLCC44
43 - 36
2 - 9
22
44
2
3
4
5
6
7
8
9
Pin Number
VQFP44
37 - 30
40 - 44
1 - 3
16
38
40
41
42
43
44
1
2
3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
Name and Function
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down opera-
tion
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high impedance inputs. Port 0 must be polarized to V
V
low-order address and data bus during access to external program and data memory. In
this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code
bytes during EPROM programming. External pull-ups are required during program verifica-
tion during which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source current because of the internal
pull-ups. Port 1 also receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51ID2 Port 1 include:
P1.0: Input/Output
T2 (P1.0): Timer/Counter 2 external count input/Clockout
XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier
P1.1: Input/Output
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
SS: SPI Slave Select
P1.2: Input/Output
ECI: External Clock for the PCA
P1.3: Input/Output
CEX0: Capture/Compare External I/O for PCA module 0
P1.4: Input/Output
CEX1: Capture/Compare External I/O for PCA module 1
P1.5: Input/Output
CEX2: Capture/Compare External I/O for PCA module 2
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in
slave mode, MISO outputs data to the master controller.
P1.6: Input/Output
CEX3: Capture/Compare External I/O for PCA module 3
SCK: SPI Serial Clock
P1.7: Input/Output:
CEX4: Capture/Compare External I/O for PCA module 4
SS
in order to prevent any parasitic current consumption. Port 0 is also the multiplexed
4289C–8051–11/05
CC
or