AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet - Page 23

• Manufacturer Part Number: AT89C51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89C51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 2
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

4289C–8051–11/05
Table 21. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
Number
TWIX2
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
PCAX2
WDX2
TWIX2
WDX2
T2X2
T1X2
T0X2
SIX2
Bit
X2
6
2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and
to enable the individual peripherals’X2’ bits. Programmed by hardware after
Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is
cleared.
PCAX2
5
SIX2
4
T2X2
3
T1X2
2
AT89C51ID2
T0X2
1
X2
0
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